Embedded computing device

1. A diving information apparatus comprising:

a first processing core configured to maintain, during a dive, dive information which concerns progress of the dive, to generate first control signals and to control a display by providing the first control signals to the display via a display interface; and

a second processing core configured to repeatedly switch from a hibernation state to an active state during the dive, to verify the dive information and to switch back to the hibernation state responsive to the dive information being verified as correct,

wherein the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.

2. The diving information apparatus according claim 1 , wherein the first processing core uses less power when in an active mode, than the second processing core when the second processing core is not in the hibernation state.

3. The diving information apparatus according claim 2 , wherein the first processing core is comprised in a microcontroller and the second processing core is comprised in a microprocessor, the microcontroller being external to the microprocessor and the microprocessor being external to the microcontroller.

4. The diving information apparatus according to claim 1 , further comprising two pressure sensors, wherein the first processing core is configured to receive pressure sensor data from both pressure sensors when the diving information apparatus is within a region of depth overlap between active ranges of the two pressure sensors, and to provide a warning to the user as a response to determining the two pressure sensors provide pressure data inconsistent with each other.

5. The diving information apparatus according to claim 1 , wherein the dive information comprises at least one of: a remaining time before ascent should begin, a remaining amount of air, messages from other divers and depth as a function of time.

6. The diving information apparatus according to claim 1 , wherein the first processing core is configured to store the dive information in a first non-volatile memory and the second processing core is configured to access the dive information in a second non-volatile memory, the first and second non-volatile memories being arranged to replicate the dive information.

7. The diving information apparatus according to claim 6 , wherein the first and second non-volatile memories are not of a same type.

8. The diving information apparatus according to claim 1 , wherein the first processing core is configured to re-boot as a response to an error state occurring during the dive, and to resume maintaining the dive information after the re-boot.

9. The diving information apparatus according to claim 1 , wherein the second processing core is configured to cause the first processing core to stop maintaining the dive information as a response to the dive information being verified as incorrect.

10. The diving information apparatus according to claim 9 , wherein the second processing core is configured to maintain the dive information for a remainder of the dive subsequent to stopping the first processing core from maintaining the dive information.

11. The diving information apparatus according to claim 1 , wherein the at least one non-volatile memory is external to the first processing core and the second processing core.

12. The diving information apparatus according to claim 1 , wherein the diving information apparatus is further configured to trigger the second processing core from the hibernation state to the active state as a response to a determination that less than a predetermined length of time remains before ascent toward a surface should start, and to use the second processing core to provide graphical warning to the user, the graphical warning being of a type the first processing core cannot provide.

13. A method in a diving information apparatus, comprising:

maintaining, by a first processing core, during a dive, dive information which concerns progress of the dive, generating, by the first processing core, first control signals and controlling, by the first processing core, a display by providing the first control signals to the display via a display interface; and

repeatedly switching, by a second processing core, from a hibernation state to an active state during the dive, verifying, by the second processing core, the dive information and switching the second processing core back to the hibernation state responsive to the dive information being verified as correct,

wherein the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.

14. The method according claim 13 , wherein the first processing core uses less power when in an active mode, than the second processing core when the second processing core is not in the hibernation state.

15. The method according claim 14 , wherein the first processing core is comprised in a microcontroller and the second processing core is comprised in a microprocessor, the microcontroller being external to the microprocessor and the microprocessor being external to the microcontroller.

16. The method according to claim 13 , wherein the diving information apparatus comprises two pressure sensors, wherein the first processing core receives pressure sensor data from both pressure sensors when the diving information apparatus is within a region of depth overlap between active ranges of the two pressure sensors, and provides a warning to the user as a response to determining the two pressure sensors provide pressure data inconsistent with each other.

17. The method according to claim 13 , wherein the dive information comprises at least one of: a remaining time before ascent should begin, a remaining amount of air, messages from other divers and depth as a function of time.

18. The method according to claim 13 , further comprising storing, by the first processing core, the dive information in a first non-volatile memory and accessing, by the second processing core, the dive information in a second non-volatile memory, the first and second non-volatile memories being arranged to replicate the dive information.

19. The method according to claim 18 , wherein the first and second non-volatile memories are not of a same type.

20. The method according to claim 13 , further comprising re-booting the first processing core as a response to an error state occurring during the dive, and resuming maintaining the dive information by the first processing core after the re-boot.

21. The method according to claim 13 , further comprising causing, by the second processing core, the first processing core to stop maintaining the dive information as a response to the dive information being verified as incorrect.

22. The method according to claim 21 , wherein the second processing core maintains the dive information for a remainder of the dive subsequent to stopping the first processing core from maintaining the dive information.

23. The method according to claim 13 , wherein the at least one non-volatile memory is external to the first processing core and the second processing core.

24. A non-transitory computer readable non-transitory medium having stored thereon a set of computer readable instructions that, when executed by at least one processor, cause a diving information apparatus to at least:

maintain, by a first processing core, during a dive, dive information which concerns progress of the dive, generate, by the first processing core, first control signals and control, by the first processing core, a display by providing the first control signals to the display via a display interface; and

repeatedly switch, by a second processing core, from a hibernation state to an active state during the dive, verify, by the second processing core, the dive information and switch the second processing core back to the hibernation state responsive to the dive information being verified as correct,

wherein the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.