IP Library › Granted Patent US 12,051,472

Granted Patent B2

US 12,051,472 · App. 16/727,794 · Granted Jul 30, 2024

Solid state drive (SSD) with in-flight erasure iteration suspension

Inventors: Justin R. Dayacap (Daly City, CA); Shantanu R. Rajwade (Santa Clara, CA); Kyung Jean Yoon (Santa Clara, CA); Ali Khakifirooz (Los Altos, CA); David J. Pelster (Longmont, CO); Yogesh B. Wakchaure (Folsom, CA); Xin Guo (San Jose, CA)

Assignee: SK hynix NAND Product Solutions Corp.

G11C16/3445 G11C16/16 G11C16/32 G11C2216/20

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Quick Facts

Patent No.: US 12,051,472
App. No.: 16/727,794
Granted: Jul 30, 2024
Kind: B2

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Abstract

An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Claims (105)

1. An apparatus, comprising:

a memory; and

a hardware processor coupled to the memory and configured at least to:

apply an erase voltage to one or more storage cells;

while applying the erase voltage to the one or more storage cells:

receive a command to suspend applying the erase voltage to the one or more storage cells;

determine that an amount of time during which the erase voltage exceeds a critical voltage meets a first predetermined threshold; and

in response to receiving the command to suspend applying the erase voltage to the one or more storage cells and determining that the amount of time during which the erase voltage exceeds the critical voltage meets the first predetermined threshold:

determine not to suspend applying the erase voltage to the one or more storage cells; and

continue to apply the erase voltage to the one or more storage cells until the one or more storage cells are erased;

apply a second erase voltage to one or more second storage cells; and

while applying the second erase voltage to the one or more second storage cells:

receive a second command to suspend applying the second erase voltage to the one or more second storage cells;

determine that the second erase voltage exceeds the critical voltage;

determine that a second amount of time during which the second erase voltage exceeds the critical voltage does not meet the first predetermined threshold; and

in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells, determining that the second erase voltage exceeds the critical voltage, and determining that the second amount of time during which the second erase voltage exceeds the critical voltage does not meet the first predetermined threshold:

continue to apply the second erase voltage to the one or more second storage cells for a first period of time; and

suspend applying the second erase voltage to the one or more second storage cells after the first period of time.

2. The apparatus of claim 1 wherein the command to suspend applying the erase voltage to the one or more storage cells is received from a solid state drive (SSD) controller.

3. The apparatus of claim 1 wherein the hardware processor is further configured to:

receive additional commands after the one or more storage cells are erased.

4. The apparatus of claim 1 , further comprising register space to store at least:

a first value of the critical voltage; and

a second value of the first predetermined threshold.

5. The apparatus of claim 1 , wherein the hardware processor is further configured to:

apply a third erase voltage to one or more third storage cells;

while applying the third erase voltage to the one or more third storage cells:

receive a third command to suspend applying the third erase voltage to the one or more third storage cells; and

determine that the third erase voltage does not exceed the critical voltage; and

in response to receiving the third command to suspend applying the third erase voltage to the one or more third storage cells and determining that the third erase voltage does not exceed the critical voltage, suspend applying the third erase voltage to the one or more third storage cells for a second period of time.

6. The apparatus of claim 5 wherein the hardware processor is further configured to:

receive additional commands during the first period of time, wherein the additional commands include one or more read commands.

7. The apparatus of claim 1 wherein the second erase voltage is constant for at least a portion of the second amount of time.

8. The apparatus of claim 1 , wherein the hardware processor is further configured to:

apply a third erase voltage to one or more third storage cells; and

while applying the third erase voltage to the one or more third storage cells:

receive a third command to suspend applying the third erase voltage to the one or more third storage cells;

determine that the third erase voltage does not exceed the critical voltage;

in response to determining that the third erase voltage does not exceed the critical voltage, determine that a count of erase suspensions has reached a threshold of erase suspensions;

in response to receiving the third command to suspend applying the third erase voltage to the one or more third storage cells and determining that the count of erase suspensions has reached the threshold of erase suspensions:

determine not to suspend applying the third erase voltage to the one or more third storage cells; and

continue to apply the third erase voltage to the one or more third storage cells until the one or more third storage cells are erased.

9. A method, comprising:

applying an erase voltage to one or more storage cells;

while applying the erase voltage to the one or more storage cells:

receiving a command to suspend applying the erase voltage to the one or more storage cells;

determining that an amount of time during which the erase voltage exceeds a critical voltage meets a first predetermined threshold; and

determining not to suspend applying the erase voltage to the one or more storage cells; and

continuing to apply the erase voltage to the one or more storage cells until the one or more storage cells are erased;

applying a second erase voltage to one or more second storage cells; and

while applying the second erase voltage to the one or more second storage cells:

receiving a second command to suspend applying the second erase voltage to the one or more second storage cells;

determining that the second erase voltage exceeds the critical voltage;

determining that a second amount of time during which the second erase voltage exceeds the critical voltage does not meet the first predetermined threshold; and

continuing to apply the second erase voltage to the one or more second storage cells for a first period of time; and

suspending applying the second erase voltage to the one or more second storage cells after the first period of time.

10. The method of claim 9 further comprising:

receiving additional commands after the one or more storage cells are erased.

11. The method of claim 9 further comprising: storing in a register space at least:

a first value of the critical voltage; and

a second value of the first predetermined threshold.

12. The method of claim 9 further comprising:

applying a third erase voltage to one or more third storage cells; and

while applying the third erase voltage to the one or more third storage cells:

receiving a third command to suspend applying the third erase voltage to the one or more third storage cells; and

determining that the third erase voltage does not exceed the critical voltage; and

in response to receiving the third command to suspend applying the third erase voltage to the one or more third storage cells and determining that the third erase voltage does not exceed the critical voltage, suspending applying the third erase voltage to the one or more third storage cells for a second period of time.

13. The method of claim 9 wherein the second erase voltage is constant for at least a portion of the second amount of time.

14. The method of claim 9 , further comprising:

applying a third erase voltage to one or more third storage cells; and

while applying the third erase voltage to the one or more third storage cells:

receiving a third command to suspend applying the third erase voltage to the one or more third storage cells;

determining that the third erase voltage does not exceed the critical voltage;

in response to determining that the third erase voltage does not exceed the critical voltage, determining that a count of erase suspensions has reached a threshold of erase suspensions;

determining not to suspend applying the third erase voltage to the one or more third storage cells; and

continuing to apply the third erase voltage to the one or more third storage cells until the one or more third storage cells are erased.

15. A non-transitory computer-readable medium containing computer executable instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:

applying an erase voltage to one or more storage cells; and