IP Library Granted Patent US 11,144,247
Granted Patent B2
US 11,144,247 · App. 16/728,599 · Granted Oct 12, 2021

Fast input/output in a content-addressable storage architecture with paged metadata

Inventors: Zvi Schneider (Tel Aviv, IL); Amitai Alkalay (Kadima, IL); Assaf Natanzon (Tel Aviv, IL)
Assignee: EMC IP Holding Company LLC
G06F3/0659G06F3/0619G06F3/0673G06F3/0689G06F12/10G06F13/1668G06F15/17331G06F2212/1032G06F2212/657G06F2213/28
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Quick Facts
Patent No.
US 11,144,247
App. No.
16/728,599
Granted
Oct 12, 2021
Kind
B2
Abstract

An aspect includes reading a first page and a corresponding second page from a storage device. The first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata. An aspect also includes reading data for a RAID stripe according to an associated physical offset in the second page, accessing a stripe counter from the second page, and comparing the stripe counter from the second page to a stripe counter held in memory. Upon determining the stripe counter from the second page is not the same, a third page is loaded, and a physical location of the data is read from the third page that provides a hash value of the data and corresponding physical location. The physical location of the data is accessed, and the second page is updated.

Claims (62)

1. A method for minimizing read amplification for input/output (IO) where metadata is not in random access memory (RAM), comprising:

reading a first page and a corresponding second page from a storage device in a dual distributed layered architecture, the first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata;

reading data for a redundant array of independent disks (RAID) stripe according to an associated physical offset in the second page;

accessing a stripe counter from the second page;

comparing the stripe counter from the second page to a stripe counter held in memory;

upon determining the stripe counter from the second page is the same as the first stripe counter held in memory:

determining the data is valid; and

reading the data according to associated physical offset in the second page and while bypassing a data module for the data;

upon determining the stripe counter from the second page is not the same:

accessing the data module, loading a third page, and reading a physical location of the data from the third page, the third page providing a hash value of the data and corresponding physical location of the data;

accessing the physical location of the data during a read operation; and

updating the second page.

2. The method of claim 1 , wherein reading the first page and the second page is performed by sending an IO request to the data module.

3. The method of claim 1 , wherein reading the first page and the second page is performed by a direct non-volatile memory over fabric (NVMEoF) read from a control module to the drives bypassing the data module, the reading performed upon determining the data is correct.

4. The method of claim 1 , wherein accessing the stripe counter is performed by sending a request to the data module.

5. The method of claim 1 , wherein upon accessing the stripe counter the method includes reading a remote direct memory access (RDMA) read via an RDMA interconnect from a relevant offset in mapped memory.

6. The method of claim 1 , further comprising:

concatenating the first page and the page to produce concatenated pages; and

storing the concatenated pages in the solid state disk.

7. The method of claim 6 , wherein reading the reading the first page and the second page includes loading the concatenated pages in a single command.

8. A system for minimizing read amplification for input/output (IO) where metadata is not in random access memory (RAM), comprising:

a memory comprising computer-executable instructions; and

a processor executing the computer-executable instructions, the computer-executable instructions when executed by the processor cause the processor to perform operations comprising:

reading a first page and a corresponding second page from a storage device in a dual distributed layered architecture, the first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata;

reading data for a redundant array of independent disks (RAID) stripe according to an associated physical offset in the second page;

accessing a stripe counter from the second page;

comparing the stripe counter from the second page to a stripe counter held in memory;

upon determining the stripe counter from the second page is the same as the first stripe counter held in memory:

determining the data is valid; and

reading the data according to associated physical offset in the second page and while bypassing a data module for the data;

upon determining the stripe counter from the second page is not the same:

accessing the data module, loading a third page, and reading a physical location of the data from the third page, the third page providing a hash value of the data and corresponding physical location of the data;

accessing the physical location of the data during a read operation; and

updating the second page.

9. The system of claim 8 , wherein reading the first page and the second page is performed by sending an IO request to the data module.

10. The system of claim 8 , wherein reading the first page and the second page is performed by a direct NVMEoF read from a control module to the drives bypassing the data module, the reading performed upon determining the data is correct.

11. The system of claim 8 , wherein accessing the stripe counter is performed by sending a request to the data module.

12. The system of claim 8 , wherein upon accessing the stripe counter, the operations further include reading an RDMA read via an RDMA interconnect from a relevant offset in mapped memory.

13. The system of claim 8 , wherein the operations further include:

concatenating the first page and the second page to create concatenated pages; and

storing the concatenated pages in the solid state disk.

14. The system of claim 13 , wherein reading the reading the first page and the second page includes loading the concatenated pages in a single command.

15. A computer program product embodied on a non-transitory computer readable medium, the computer program product including instructions that, when executed by a computer causes the computer to perform operations comprising:

reading a first page and a corresponding second page from a storage device in a dual distributed layered architecture, the first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata;

reading data for a redundant array of independent disks (RAID) stripe according to an associated physical offset in the second page;

accessing a stripe counter from the second page;

comparing the stripe counter from the second page to a stripe counter held in memory;

upon determining the stripe counter from the second page is the same as the first stripe counter held in memory:

determining the data is valid; and

reading the data according to associated physical offset in the second page and while bypassing a data module for the data;

upon determining the stripe counter from the second page is not the same:

accessing the data module, loading a third page, and reading a physical location of the data from the third page, the third page providing a hash value of the data and corresponding physical location of the data;

accessing the physical location of the data during a read operation; and

updating the second page.

16. The computer program product of claim 15 , wherein reading the first page and the second page is performed by sending an input/output (IO) request to the data module.

17. The computer program product of claim 15 , wherein reading the first page and the second page is performed by a direct NVMEoF read from a control module to the drives bypassing the data module, the reading performed upon determining the data is correct.

18. The computer program product of claim 15 , wherein accessing the stripe counter is performed by sending a request to the data module.

19. The computer program product of claim 15 , wherein upon accessing the stripe counter the operations further include reading an RDMA read via an RDMA interconnect from a relevant offset in mapped memory.

20. The computer program product of claim 15 , wherein the operations further include:

concatenating the first page and the second page to produce concatenated pages; and

storing the concatenated pages in the solid state disk;

wherein reading the first page and the second page includes loading the concatenated pages in a single command.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052216/0758) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0680 →
RELEASE OF SECURITY INTEREST AF REEL 052243 FRAME 0773 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0152 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 26, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052243/0773 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 24, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052216/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: SCHNEIDER, ZVI; ALKALAY, AMITAI; NATANZON, ASSAF
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 051608/0036 →