Memory arrays and methods used in forming a memory array

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein, conductor-material contacts being directly against the channel material of individual of the channel-material strings;

forming first insulator material directly above the conductor-material contacts, the first insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide;

forming second insulator material directly above the first insulator material and the conductor-material contacts, the second insulator material being devoid of each of the (a) and (b);

forming third insulator material directly above the second insulator material, the first insulator material, and the conductor-material contacts; the third insulator material comprising at least one of the (a) and (b); and

forming at least one horizontally-elongated isolation structure in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions.

2. The method of claim 1 wherein the first insulator material is directly against the conductor-material contacts.

3. The method of claim 1 wherein the second insulator material is directly against the first insulator material.

4. The method of claim 1 wherein the third insulator material is directly against the second insulator material.

5. The method of claim 1 wherein:

the first insulator material is directly against the conductor-material contacts;

the second insulator material is directly against the first insulator material; and

the third insulator material is directly against the second insulator material.

6. The method of claim 1 wherein the first and third insulator materials are of different compositions relative one another.

7. The method of claim 1 wherein the first and third insulator materials are of the same composition relative one another.

8. The method of claim 1 being devoid of each of the (a) and (b) vertically between the first and third insulator materials.

9. The method of claim 1 wherein the first insulator material comprises the (a).

10. The method of claim 1 wherein the first insulator material comprises the (b).

11. The method of claim 1 wherein the third insulator material comprises the (a).

12. The method of claim 1 wherein the third insulator material comprises the (b).

13. The method of claim 1 wherein the first tiers comprise sacrificial material, and further comprising:

forming horizontally-elongated trenches into the stack between the memory-block regions;

through the trenches, isotropically etching away and replacing the sacrificial material that is in the first tiers with conducting material of individual conductive lines; and

forming intervening material in the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions.

14. The method of claim 1 comprising forming conductive vias through the first and second insulator materials that are individually directly against individual of the conductor-material contacts.

15. The method of claim 1 comprising forming the at least one isolation structure to have a higher top than tops of the conductor-material contacts.

16. The method of claim 1 wherein the isolation structure comprises a lower horizontally-elongated insulator material and an upper horizontally-elongated insulator material there-above, the upper insulator material comprising at least one of the (a) and (b), the lower insulator material being devoid of each of the (a) and (b).

17. The method of claim 14 wherein forming the conductive vias comprises:

after forming the isolation structure, forming conductive via openings through the second and first insulator materials to individual of the conductor-material contacts; and

forming conductive material in the conductive via openings that is directly against the individual conductor-material contacts to form conductive vias.

18. The method of claim 17 wherein forming the conductive via openings comprises:

anisotropically etching through the second insulator material selectively relative to the first insulator material using a first etching chemistry to stop on or in the first insulator material; and

etching through the first insulator material using a second etching chemistry that is different from the first etching chemistry to expose the individual conductor-material contacts.

19. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein, conductor-material contacts being directly against the channel material of individual of the channel-material strings;

forming first insulator material directly above the conductor-material contacts, the first insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide;

forming second insulator material directly above the first insulator material and the conductor-material contacts, the second insulator material being devoid of each of the (a) and (b);

forming third insulator material directly above the second insulator material, the first insulator material, and the conductor-material contacts; the third insulator material comprising at least one of the (a) and (b); and

forming conductive vias through the first and second insulator materials that are individually directly against individual of the conductor-material contacts.

20. The method of claim 19 wherein forming the conductive vias comprises:

forming conductive via openings through the second and first insulator materials to individual of the conductor-material contacts; and

forming conductive material in the conductive via openings that is directly against the individual conductor-material contacts.

21. The method of claim 19 wherein the alternating first and second tiers comprise memory-block regions, and further comprising:

forming at least one horizontally-elongated isolation structure through the first and second insulator materials and in a top part of the stack in individual of the memory-block regions.

22. The method of claim 20 comprising removing the third insulator material before forming the conductive via openings whereby the conductive via openings are not formed through the third insulator material.

23. The method of claim 20 wherein forming the conductive via openings comprises:

anisotropically etching through the second insulator material selectively relative to the first insulator material using a first etching chemistry to stop on or in the first insulator material; and

etching through the first insulator material using a second etching chemistry that is different from the first etching chemistry to expose the individual conductor-material contacts.

24. The method of claim 21 comprising forming the isolation structure to comprise a lower horizontally-elongated insulator material and an upper horizontally-elongated insulator material there-above, the upper insulator material comprising at least one of the (a) and (b), the lower insulator material being devoid of each of the (a) and (b).

25. The method of claim 21 comprising forming the at least one isolation structure to have a higher top than tops of the conductor-material contacts.

26. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein; and

forming at least one horizontally-elongated isolation structure in a top part of the stack in individual of the memory-block regions, the isolation structure comprising a lower horizontally-elongated insulator material and an upper horizontally-elongated insulator material there-above, the upper insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide, the lower insulator material being devoid of each of the (a) and (b).

27. The method of claim 26 wherein the first insulator material comprises the (a).

28. The method of claim 26 wherein the first insulator material comprises the (b).

29. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein, conductor-material contacts being directly against the channel material of individual of the channel-material strings, at least one horizontally-elongated isolation structure in a top part of the stack in individual of the memory-block regions;

forming insulator material directly above the conductor-material contacts and the at least one isolation structure, the insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; and

forming conductive vias through the insulator material that are individually directly against individual of the conductor-material contacts.

30. The method of claim 29 wherein the insulator material is directly against the conductor-material contacts.

31. The method of claim 29 wherein the insulator material is directly against the at least one isolation structure.

32. The method of claim 29 wherein, the insulator material is directly against the conductor-material contacts; and

the insulator material is directly against the at least one isolation structure.

33. The method of claim 29 wherein the insulator material comprises the (a).

34. The method of claim 29 wherein the insulator material comprises the (b).

35. The method of claim 29 comprising forming insulating material directly above the insulator material, the insulating material being devoid of each of the (a) and (b), the forming of the conductive vias comprising:

forming conductive via openings through the insulating material and the insulator material to individual of the conductor-material contacts; and

forming conductive material in the conductive via openings that is directly against the individual conductor-material contacts; and

the forming of the conductive via openings comprising:

anisotropically etching through the insulating material selectively relative to the insulator material using a first etching chemistry to stop on or in the insulator material; and

etching through the insulator material using a second etching chemistry that is different from the first etching chemistry to expose the individual conductor-material contacts.

36. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells in the stack, conductor-material contacts being directly against the channel material of individual of the channel-material strings; and

an insulator material directly against tops of the conductor-material contacts, the insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide.

37. The memory array of claim 36 wherein the insulator material comprises the (a).

38. The memory array of claim 36 wherein the insulator material comprises the (b).

39. A memory array comprising strings of memory cells, comprising:

laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells in the stack; and

at least one horizontally-elongated isolation structure in a top part of the stack in individual of the memory blocks, the isolation structure comprising a lower horizontally-elongated insulator material and an upper horizontally-elongated insulator material there-above, the upper insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide, the lower insulator material being devoid of each of the (a) and (b).

40. The memory array of claim 39 wherein the upper insulator material comprises the (a).

41. The memory array of claim 39 wherein the upper insulator material comprises the (b).

42. The memory array of claim 39 wherein the at least one isolation structure is laterally-between two immediately-laterally adjacent select gates in the individual memory blocks.