Method of high speed and dynamic configuration of a transceiver system
A field-programmable gate array includes a memory, a firmware state machine, a register, and an interconnect structure. The memory is configured to store a plurality of configurations. Each of the plurality of configurations has at least one parameter associated therewith. The firmware state machine is configured to read the parameters stored in the memory. The register is configured to have the parameters associated with the plurality of configurations written thereto. The interconnect structure is configured to transmit the parameters between the firmware state machine and the register. The interconnect structure is configured to receive the parameters associated with the plurality of the configurations simultaneously and the interconnect structure is configured to transmit the received parameters associated with the plurality of configurations to the register simultaneously.
1. A field-programmable gate array comprising:
a memory configured to store a plurality of configurations including at least a first configuration and a second configuration, each of the plurality of configurations having at least one parameter associated therewith;
a firmware state machine configured to read the parameters stored in the memory;
a register configured to have the parameters associated with the plurality of configurations written thereto; and
an interconnect structure configured to transmit the parameters between the firmware state machine and the register, the interconnect structure being configured to receive the parameters associated with the first configuration and the second configuration simultaneously and the interconnect structure being configured to transmit the received parameters associated with the first configuration and the second configuration to the register simultaneously.
2. The field-programmable gate array according to claim 1 , wherein
the memory has a number of memory spaces corresponding to a number of the plurality of configurations.
3. The field-programmable gate array according to claim 2 , wherein
the register has a number of register spaces corresponding to the number of the plurality of configurations.
4. The field-programmable gate array according to claim 3 , wherein
the interconnect structure has a plurality of primary interfaces, each of the plurality of primary interfaces being connected to a different one of the plurality of configurations stored in the memory.
5. The field-programmable gate array according to claim 4 , wherein
the interconnect structure has a plurality of secondary interfaces, each of the plurality of secondary interfaces being connected to a different one of the plurality of primary interfaces.
6. The field-programmable gate array according to claim 5 , wherein
each of the plurality of register spaces is connected to a different one of the plurality of secondary interfaces.
7. The field-programmable gate array according to claim 1 , wherein
a total configuration time of the field-programmable gate array is an amount of time to read one of the plurality of configurations from the memory and write the one of the plurality of configurations to the register.
8. A transceiver system for a satellite communication system, comprising:
a circuit board;
a processor mounted on the circuit board; and
the field-programmable gate array of claim 1 mounted on the circuit board and connected to the processor.
9. A transceiver system for a satellite communication system, comprising:
a circuit board;
a processor mounted on the circuit board; and
a plurality of the field-programmable gate arrays of claim 1 mounted on the circuit board and connected to the processor.
10. The transceiver system according to claim 9 , wherein
each of the plurality of the field-programmable gate arrays is connected to the processor by a different bus.
11. The transceiver system according to claim 10 , wherein
a total configuration time of the board is an amount of time to configure one of the plurality of field-programmable gate arrays.
12. The transceiver system according to claim 10 , wherein
the plurality of field-programmable gate arrays are configured to be configured in parallel.
13. The transceiver system according to claim 9 , wherein
each of the plurality of field programmable gate arrays is connected to a switch, the switch being connected to the processor.
14. A method of configuring a field-programmable gate array, comprising the steps of
reading a first parameter associated with a first configuration stored in a memory of the field-programmable gate array;
reading a second parameter associated with a second configuration stored in the memory of the field-programmable gate array, the second parameter being read simultaneously with the first parameter;
writing the first parameter associated with the first configuration to a first register space of a register; and
writing the second parameter associated with the second configuration to a second register space of the register, the second parameter being written simultaneously with the first parameter.
15. The method of configuring a field-programmable gate array according to claim 14 , wherein
the total configuration time for configuring a plurality of parameters of the field-programmable gate array is an amount of time to read and write one of the plurality of parameters to one register space of the register.
16. A method of configuring a field-programmable gate array board, the board having a plurality of field-programmable gate arrays configured in accordance with claim 14 , the method comprising the steps of
configuring each of the plurality of field-programmable gate arrays in parallel.
17. The method of configuring a field-programmable gate array board according to claim 16 , wherein
a total configuration time to configure the plurality of field-programmable gate arrays is an amount of time to configure one of the field-programmable gate arrays.
18. The method of configuring a field-programmable gate array board according to claim 17 , wherein
each of the plurality of field-programmable gate arrays is connected to a processor by a different bus.
19. The field-programmable gate array according to claim 1 , wherein
the memory includes a first configuration space configured to store the first configuration and a second configuration space configured to store the second configuration, and
the interconnect structure is configured to simultaneously receive at least one parameter associated with the first configuration from the first configuration space and least one parameter associated with the second configuration from the second configuration space.
20. The field-programmable gate array according to claim 1 , wherein
the register includes a first configuration space configured to have parameters of the first configuration written thereto and a second configuration space configured to have parameters of the second configuration written thereto, and
the interconnect structure is configured to simultaneously transmit at least one parameter associated with the first configuration to the first configuration space and at least one parameter associated with the second configuration to the second configuration space.