IP Library Granted Patent US 11,132,077
Granted Patent B2
US 11,132,077 · App. 16/733,190 · Granted Sep 28, 2021

Method of routing in a singular direction first traces that are electrically coupled to respective rows of an array of touch sensors between respective second traces that are electrically coupled to respective columns of the array

Inventor: Ilya Daniel Rosenberg (Mountain View, CA)
Assignee: SENSEL, INC.
G06F3/041G02F1/1343H05K1/0353H05K1/115H05K1/117H05K1/181H05K3/30H05K3/303G06F2203/04102G06F2203/04103G06F2203/04105H05K2201/0154H05K2201/10151
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,132,077
App. No.
16/733,190
Granted
Sep 28, 2021
Kind
B2
Abstract

A method for improving flexibility of a circuit board, e.g., comprising a touch-based sensor, and reducing manufacturing costs by eliminating routing around a border of the touch-based sensor is presented herein. The method comprises forming an array of touch sensors on a first side of the circuit board, in which portions of the circuit board located between three edges of the circuit board and a border of the array of touch sensors exclude traces; and forming first traces between respective second traces in a singular direction on a second side of the circuit board, in which the first traces are electrically coupled, using a first group of vias, to respective rows of the array of touch sensors, and the second traces are electrically coupled, using a second group of vias, to respective columns of the array of touch sensors.

Claims (32)

1. A method, comprising:

forming an array of touch sensors on a first side of a circuit board, wherein portions of the circuit board located between three edges of the circuit board and a border of the array of touch sensors exclude traces; and

forming first traces between second traces in a singular direction on a second side of the circuit board, wherein the first traces are electrically coupled, using a first group of vias, to respective rows of the array of touch sensors, wherein the second traces are electrically coupled, using a second group of vias, to respective columns of the array of touch sensors, and wherein a first portion of the second traces are formed between a second portion of the first traces in the singular direction on the second side of the circuit board.

2. The method of claim 1 , further comprising:

embedding resistors between respective traces of the first traces.

3. The method of claim 2 , wherein the embedding comprises:

printing, via respective thick-film carbon depositions, the resistors between the respective traces of the first traces.

4. The method of claim 1 , further comprising:

embedding resistors between respective traces of the second traces.

5. The method of claim 4 , wherein the embedding comprises:

printing, via respective thick-film carbon depositions, the resistors between the respective traces of the second traces.

6. The method of claim 1 , further comprising:

attaching, to a tail portion of the circuit board, surface mount resistors; and

electrically connecting the surface mount resistors to respective traces of at least one of the first traces or the second traces.

7. The method of claim 1 , further comprising:

printing, on a tail portion of the circuit board via a thick-film carbon deposition, resistors; and

electrically connecting the resistors to respective traces of at least one of the first traces or the second traces.

8. The method of claim 1 , wherein the forming of the first traces between the second traces comprises forming the first traces between the second traces based on a 1.0 mm pitch between the first traces and the second traces.

9. The method of claim 1 , wherein the forming of the first traces between the second traces comprises forming the first traces between the second traces based on a 1.25 mm pitch between the first traces and the second traces.

10. A two-layer printed circuit board (PCB), comprising:

a tactile sensor comprising an array of touch sensors that has been formed on a first side of the two-layer PCB, wherein traces are absent between three edges of the two-layer PCB and a defined border of the array of touch sensors; and

first traces routed between second traces on a second side of the two-layer PCB in a singular direction, wherein the first traces are electrically coupled to respective rows of the array of touch sensors, wherein the second traces are electrically coupled to respective columns of the array of touch sensors, and wherein a first portion of the second traces are routed between a second portion of the first traces.

11. The two-layer PCB of claim 10 , wherein the touch sensors comprise force-based sensors.

12. The two-layer PCB of claim 10 , wherein the touch sensors comprise a variable impedance array (VIA) of sensors comprising variable impedance elements that interconnect with respective row and column cross points of the VIA of sensors.

13. The two-layer PCB of claim 10 , wherein the first traces are electrically coupled to the respective rows utilizing respective vias connecting the first traces to the respective rows.

14. The two-layer PCB of claim 10 , wherein the second traces are electrically coupled to the respective columns utilizing respective vias connecting the second traces to the respective columns.

15. The two-layer PCB of claim 10 , wherein resistors are connected between respective traces of the first traces.

16. The two-layer PCB of claim 10 , wherein resistors are connected between respective traces of the second traces.

17. The two-layer PCB of claim 10 , wherein surface mount resistors of a tail portion of the two-layer PCB are connected to respective traces of at least one of the first traces or the second traces.

18. The two-layer PCB of claim 10 , wherein a tail portion of the two-layer PCB comprises pins that are connected to respective traces of at least one of the first traces or the second traces.

19. The two-layer PCB of claim 10 , wherein the first side of the two-layer PCB comprises Kapton.

20. The two-layer PCB of claim 10 , wherein the first side of the two-layer PCB comprises FR4.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2025
From: SENSEL, INC
To: CIRQUE CORPORATION
Reel/Frame 072018/0359 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2020
From: ROSENBERG, ILYA DANIEL
To: SENSEL, INC.
Reel/Frame 051405/0896 →
Continuity (2)
Provisional Application 62788669 · Jan 4, 2019
Related Publication 20200218373A1 · Jul 9, 2020