Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
A global front end scheduler to schedule instruction sequences to a plurality of virtual cores implemented via a plurality of partitionable engines. The global front end scheduler includes a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed, a bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks, and a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread.
1. A global front end scheduler comprising:
a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed;
the bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks;
a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread; and
a circuit to schedule instruction sequences to a plurality of virtual cores implemented via a plurality of partitionable engines.
2. The global front end scheduler of claim 1 , wherein an allocation thread pointer from the set of allocation thread pointers identifies a bucket interval in the matrix of buckets that are continuous as the set of buckets for a respective thread.
3. The global front end scheduler of claim 2 , wherein the circuit updates an allocation pointer to point to a next bucket in the set of buckets in the bucket interval in a round robin fashion.
4. The global front end scheduler of claim 2 , wherein the circuit updates a retirement thread pointer to point to a next bucket in the bucket interval as each bucket for an associated thread is retired.
5. The global front end scheduler of claim 2 , wherein when a new bucket is assigned for a block in the bucket interval, the circuit copies an inheritance vector into the new bucket from a previous bucket for the thread.
6. The global front end scheduler of claim 5 , wherein destination registers for the block of the new bucket are overwritten in the copied inheritance vector.
7. A system for processing blocks of instructions, the system comprising:
a set of processing resources that are partitionable into a set of virtual cores; and
a processing pipeline coupled to the set of processing resources, the processing pipeline including a global front end scheduler, the global front end scheduler including, a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed,
the bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks,
a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread, and
a circuit to schedule instruction sequences to the set of virtual cores implemented via a plurality of partitionable engines.
8. The system of claim 7 , wherein an allocation thread pointer from the set of allocation thread pointers identifies a bucket interval in the matrix of buckets that are continuous as the set of buckets for a respective thread.
9. The system of claim 8 , wherein the circuit updates an allocation pointer to point to a next bucket in the set of buckets in the bucket interval in a round robin fashion.
10. The system of claim 8 , wherein the circuit updates a retirement thread pointer to point to a next bucket in the bucket interval as each bucket for an associated thread is retired.
11. The system of claim 8 , wherein when a new bucket is assigned for a block in the bucket interval, the circuit copies an inheritance vector into the new bucket from a previous bucket for the thread.
12. The system of claim 11 , wherein destination registers for the block of the new bucket are overwritten in the copied inheritance vector.
13. A computer system for processing blocks of instructions, the computer system comprising:
a memory portioned int a plurality of memory fragments; and
a processor including a set of processing resources that are partitionable into a set of virtual cores, and a processing pipeline coupled to the set of processing resources, the processing pipeline including a global front end scheduler, the global front end scheduler including, a thread allocation array to store a set of allocation thread pointers to point to a set
of buckets in a bucket buffer in which execution blocks for respective threads are placed,
the bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks,
a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread, and
a circuit to schedule instruction sequences to the set of virtual cores implemented via a plurality of partitionable engines.
14. The computer system of claim 13 , wherein an allocation thread pointer from the set of allocation thread pointers identifies a bucket interval in the matrix of buckets that are continuous as the set of buckets for a respective thread.
15. The computer system of claim 14 , wherein the circuit updates an allocation pointer to point to a next bucket in the set of buckets in the bucket interval in a round robin fashion.
16. The computer system of claim 14 , wherein the circuit updates a retirement thread pointer to point to a next bucket in the bucket interval as each bucket for an associated thread is retired.
17. The computer system of claim 14 , wherein when a new bucket is assigned for a block in the bucket interval, the circuit copies an inheritance vector into the new bucket from a previous bucket for the thread.
18. The computer system of claim 17 , wherein destination registers for the block of the new bucket are overwritten in the copied inheritance vector.