Single-chip series connected VCSEL array
Methods, devices and systems are described for enabling a series-connected, single chip vertical-cavity surface-emitting laser (VCSEL) array. In one aspect, the single chip includes one or more non-conductive regions one the conductive layer to produce a plurality of electrically separate conductive regions. Each electrically separate region may have a plurality of VCSEL elements, including an anode region and a cathode region connected in series. The chip is connected to a sub-mount with a metallization pattern, which connects each electrically separate region on the conductive layer in series. In one aspect, the metallization pattern connects the anode region of a first electrically separate region to the cathode region of a second electrically separate region. The metallization pattern may also comprise cuts that maintain electrical separation between the anode and cathode regions on each conductive layer region, and that align with the etched regions.
1. A series-connected vertical-cavity surface-emitting laser (VCSEL) array, comprising:
a single semiconductor die including a semiconductor substrate and a conductive cathode layer, the conductive cathode layer including a series of adjoining electrically conductive regions, each electrically conductive region separated from an adjoining electrically conductive region by a non-conductive isolation region, each electrically conductive region including a plurality of VCSEL elements having anode contacts and a plurality grounding elements having common cathode contacts, each grounding element connected directly to the conductive cathode layer to form a common ground connection; and
a sub-mount including a metallization pattern serially connecting each electrically conductive region to an adjoining electrically conductive region by connecting to the anode contacts of each electrically conductive region and then connecting the cathode contacts of each electrically conductive region to the anode contacts of the adjoining electrically conductive region while maintaining electrical separation between the anode contacts and the cathode contacts on each electrically conductive region and each adjoining electrically conductive region so that current flows from the common ground connection of each electrically conductive region of a first plurality of VCSEL elements to the anode contacts of the adjoining electrically conductive region so as to connect a first plurality of VCSEL elements in each electrically conductive region in series to a second plurality of VCSEL elements in the adjoining electrically conductive region.
2. The VCSEL array of claim 1 , wherein the semiconductor substrate is at least a semi-insulating material.
3. The VCSEL array of claim 1 , wherein the non-conductive isolation region is formed by one or more of etching and ion implants on the conductive cathode layer.
4. The VCSEL array of claim 1 , wherein the non-conductive isolation region include an etch pattern with cleaved or diced edges.
5. The VCSEL array of claim 1 , wherein the metallization pattern includes a first metal contact pattern to match locations of the anode contacts in each electrically conductive region and a second metal contact pattern to match locations of the cathode contacts in each electrically conductive region to the locations of anode contacts in the adjoining electrically conductive region.
6. The VCSEL array of claim 5 , wherein the locations of the cathode contacts within each electrically conductive region are positioned in an area that surrounds but is physically separate from at least a portion of the locations of the anode contacts in each electrically conductive region so the first metal contact pattern does not short to the second metal contact pattern.
7. The VCSEL array of claim 1 , wherein the anode contacts and the cathode contacts are formed on a same side of the single semiconductor die to facilitate making all electrical connections through a single flip-chip bond step.
8. The VCSEL array of claim 1 , wherein the sub-mount and the single semiconductor die are connected through flip-chip bonding.
9. The VCSEL array of claim 1 , wherein individual VCSEL elements among the plurality of VCSEL elements are electrically connectable to external driver circuitry through a direct bond to matching metallic contacts on a driver integrated circuit substrate of the external driver circuitry.
10. The VCSEL array of claim 1 , wherein the anode contacts of each VCSEL element connected by the conductive cathode layer within an area on the single semiconductor die are electrically connected by a first metal layer and the cathode contacts connected by the conductive cathode layer within the area are electrically connected by a second metal layer, and wherein the first metal layer is not directly connected to the second metal layer.
11. The VCSEL array of claim 1 , wherein the sub-mount is a printed wiring board or patterned circuit.
12. The VCSEL array of claim 1 , wherein the sub-mount is an active integrated circuit that provides power, temperature control or other electronic functions for the single semiconductor die.