IP Library Granted Patent US 11,573,138
Granted Patent B2
US 11,573,138 · App. 16/737,708 · Granted Feb 7, 2023

Doubly interlaced sensor array and method to support low power counting and identification

Inventor: Russell Calvarese (Stony Brook, NY)
Assignee: Zebra Technologies Corporation
G01L1/225G01D5/24G01V8/20H05K1/11
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Quick Facts
Patent No.
US 11,573,138
App. No.
16/737,708
Granted
Feb 7, 2023
Kind
B2
Abstract

Systems and methods for providing low-power sensing, identification, and sweep detection for items on a sensor mat are provided. Item detection sensors are provided in grid on a sensor mat. A first subset of the item detection sensors are sensed at a first time, and a second subset of the item detection sensors are sensed at a second time. The item detection sensors of the first and second subsets are chosen such that they span the surface of the sensor mat, and so that the sensors of the chosen subsets include all of the sensors of the mat after multiple sensing steps have been completed.

Claims (18)

1. A sensor mat comprising:

a first substrate configured to form a lower portion of the mat;

a second substrate configured to form an upper portion of the mat;

a first plurality of electrical traces positioned between the first substrate and the second substrate, each of the first plurality of electrical traces being substantially parallel to each other of the first plurality of electrical traces;

a second plurality of electrical traces positioned between the first substrate and the second substrate, each of the second plurality of electrical traces being substantially parallel to each other of the second plurality of electrical traces,

the first plurality of electrical traces and the second plurality of electrical traces being laid out such that each of the first plurality of electrical traces at least one of overlaps and passes under each of the second plurality of electrical traces, the first plurality of electrical traces and the second plurality of electrical traces being further laid out such that each of the second plurality of electrical traces at least one of overlaps and passes under each of the first plurality of electrical traces;

a drive circuit communicatively coupled to each of the first plurality of electrical traces and the second plurality of electrical traces, the drive circuit including a first plurality of banks configured to interface the first plurality of electrical traces and a second plurality of banks configured to interface the second plurality of electrical traces,

wherein one of the first plurality of banks is configured to transmit sense-data to a first sub-plurality of electrical traces and one of the second plurality of banks is configured to receive sense-data from a second sub-plurality of electrical traces, the first sub-plurality of electrical traces being formed by a non-sequential series of some of the first plurality of electrical traces, the second sub-plurality of electrical traces being formed by a non-sequential series of some of the second plurality of electrical traces.

2. The sensor mat of claim 1 , wherein each of the first plurality of electrical traces is positioned orthogonally to each of the second plurality of electrical traces.

3. The sensor mat of claim 1 , wherein the sensor mat includes a wired power input.

4. The sensor mat of claim 1 , wherein at least three of the first sub-plurality of electrical traces are equally separated from each other by a first number of some of the first plurality of electrical traces.

5. The sensor mat of claim 4 , wherein at least three of the second sub-plurality of electrical traces are equally separated from each other by a second number of some of the second plurality of electrical traces.

6. The sensor mat of claim 1 , wherein a ratio of the first sub-plurality of electrical traces to the second sub-plurality of electrical traces is equal to a ratio of the first plurality of electrical traces to the second plurality of electrical traces.

7. The sensor mat of claim 1 further comprising:

a controller communicatively coupled to the drive circuit, the controller being configured to:

cause the one of the first plurality of banks to transmit sense-data to the first sub-plurality of electrical traces in a first mode of operation; and

responsive to a transition from the first mode of operation to a second mode of operation, cause the one of the first plurality of banks to transmit sense-data to a third sub-plurality of electrical traces, the third sub-plurality of electrical traces being formed by a sequential series of some of the first plurality of electrical traces.

8. The sensor mat of claim 7 , wherein, in the second mode of operation, the controller is further configured to cause the one of the second plurality of banks to receive sense-data from a fourth sub-plurality of electrical traces, the fourth sub-plurality of electrical traces being formed by a sequential series of some of the second plurality of electrical traces.

Assignments (4)
SECURITY INTEREST Recorded Apr 12, 2021
From: ZEBRA TECHNOLOGIES CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 056471/0906 →
RELEASE OF SECURITY INTEREST - 364 - DAY Recorded Mar 5, 2021
From: JPMORGAN CHASE BANK, N.A.
To: ZEBRA TECHNOLOGIES CORPORATION; LASER BAND, LLC; TEMPTIME CORPORATION
Reel/Frame 056036/0590 →
SECURITY INTEREST Recorded Sep 1, 2020
From: ZEBRA TECHNOLOGIES CORPORATION; LASER BAND, LLC; TEMPTIME CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 053841/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2020
From: CALVARESE, RUSSELL
To: ZEBRA TECHNOLOGIES CORPORATION
Reel/Frame 053640/0706 →