IP Library Granted Patent US 10,997,046
Granted Patent B2
US 10,997,046 · App. 16/738,264 · Granted May 4, 2021

Integrity check staging

Inventors: Yosuke Katayama (Yokohama, JP); Yuichiro Seto (Yokohama, JP); Ken Sasaki (Yokohama, JP)
Assignee: LENOVO (SINGAPORE) PTE. LTD.
G06F11/2284G06F11/2221G06F13/20
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Quick Facts
Patent No.
US 10,997,046
App. No.
16/738,264
Granted
May 4, 2021
Kind
B2
Abstract

An information processing apparatus includes a BIOS storage unit that stores at least a Basic Input Output System (BIOS) program, a main controller that starts up an operating system by executing the BIOS program, and a sub-controller that manages peripheral apparatuses and accesses the BIOS storage unit, in which the sub-controller includes a digest computation unit that computes a digest value on the basis of BIOS program data stored in the BIOS storage unit in parallel to execution of a process in the main controller, and in which the main controller determines validity of the BIOS program on the basis of the digest value.

Claims (19)

1. An information processing apparatus comprising:

a BIOS storage unit that stores at least a Basic Input Output System (BIOS) program;

a main controller that starts up an operating system by executing the BIOS program; and

a sub-controller that manages peripheral apparatuses and from which the BIOS storage unit is accessible,

wherein the sub controller includes a digest computation unit that computes a digest value on the basis of BIOS program data stored in the BIOS storage unit in parallel with execution of a process in the main controller, and

wherein the main controller determines validity of the BIOS program on the basis of the digest value.

2. The information processing apparatus according to claim 1 ,

wherein the BIOS storage unit is accessible from the main controller via the sub-controller.

3. The information processing apparatus according to claim 1 ,

wherein the digest computation unit computes the digest value in response to starting of an operation of the sub-controller.

4. The information processing apparatus according to claim 1 ,

wherein the digest computation unit computes the digest value in response to a digest value computation request from the main controller.

5. The information processing apparatus according to claim 1 ,

wherein the digest computation unit computes the digest value in response to starting of an operation of the sub-controller in a first mode wherein power is supplied from an external power source, and computes the digest value in response to a digest value computation request from the main controller in a second mode wherein power is supplied from a built-in battery of the information processing apparatus.

6. The information processing apparatus according to claim 1 ,

wherein the main controller acquires the digest value from the sub-controller, compares the acquired digest value with a valid digest value, and determines the validity of the BIOS program on the basis of a comparison result between the acquired and valid digest values.

7. The information processing apparatus according to claim 1 ,

wherein the sub-controller compares the digest value computed by the digest computation unit with a valid digest value, and transmits a comparison result between the computed and valid digest values to the main controller, and

wherein the main controller acquires the comparison result from the sub-controller, and determines the validity of the BIOS program on the basis of the acquired comparison result.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: LENOVO PC INTERNATIONAL LIMITED
To: LENOVO SWITZERLAND INTERNATIONAL GMBH
Reel/Frame 069870/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2022
From: LENOVO (SINGAPORE) PTE LTD
To: LENOVO PC INTERNATIONAL LIMITED
Reel/Frame 060638/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2020
From: KATAYAMA, YOSUKE; SETO, YUICHIRO; SASAKI, KEN
To: LENOVO (SINGAPORE) PTE. LTD.
Reel/Frame 051465/0609 →