IP Library Granted Patent US 11,061,838
Granted Patent B1
US 11,061,838 · App. 16/738,446 · Granted Jul 13, 2021

System and method for graphics processing unit management infrastructure for real time data collection

Inventors: Chitrak Gupta (Bangalore, IN); Rama Bisa (Bangalore, IN); Rajeshkumar Patel (Bangalore, IN); Chandrasekhar Puthilathe (Bangalore, IN); John R. Palmer (Georgetown, TX); Akkiah Maddukuri (Austin, TX); Pavan Gavvala (Bangalore, IN)
Assignee: Dell Products L.P.
G06F13/20G06F13/4022G06F13/4282G06T1/20G06F2213/0026
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Quick Facts
Patent No.
US 11,061,838
App. No.
16/738,446
Granted
Jul 13, 2021
Kind
B1
Abstract

An information handling system includes a first graphics processing unit (GPU) with a first high-speed interface, a second GPU with a second high-speed interface coupled to the first high-speed interface, and a baseboard management controller (BMC). The first GPU is configured to receive a command to provide management data to the BMC, and to provide first management data associated with the first GPU to the first GPU via the first high-speed interface in response to receiving the command. The second GPU is configured to receive the command, to receive the first management data via the second high-speed interface in response to receiving the command, and to provide the first management data and second management data associated with the second GPU to the BMC in further response to the command.

Claims (49)

1. An information handling system, comprising:

a first graphics processing unit (GPU) including a first high-speed interface;

a second GPU including a second high-speed interface coupled to the first high-speed interface; and

a baseboard management controller (BMC);

wherein:

the first GPU is configured to receive a command to provide management data to the BMC, and to provide first management data associated with the first GPU to the second GPU via the first high-speed interface in response to receiving the command; and

the second GPU is configured to receive the command, to receive the first management data via the second high-speed interface in response to receiving the command, and to provide the first management data and second management data associated with the second GPU to the BMC in further response to the command.

2. The information handling system of claim 1 , wherein the first GPU includes a first management data buffer and the second GPU includes a second management data buffer.

3. The information handling system of claim 2 , wherein the second GPU is further configured to store the first management data in a first location of the second management data buffer and to store the second management data in a second location of the second management data buffer.

4. The information handling system of claim 3 , wherein in further response to the command, the second GPU is configured to provide the second management data to the first GPU via the second high-speed interface.

5. The information handling system of claim 4 , wherein the first GPU is further configured to store the first management data in a first location of the first management data buffer and to store the second management data in a second location of the first management data buffer.

6. The information handling system of claim 1 , wherein the BMC includes a third high-speed interface coupled to the second high-speed interface.

7. The information handling system of claim 6 , wherein the BMC is configured to receive the first management data and the second management data via the third high-speed interface.

8. The information handling system of claim 1 , wherein the BMC includes a first low-speed interface and the second GPU includes a second low-speed interface coupled to the first low-speed interface.

9. The information handling system of claim 8 , wherein the BMC is configured to receive the first management data and the second management data via the first low-speed interface.

10. The information handling system of claim 9 , wherein the first GPU includes a third low-speed interface coupled to the first low-speed interface, the first GPU receives the command via the third low-speed interface, and the second GPU receives the command via the second low-speed interface.

11. A method, comprising:

receiving, by a first graphics processing unit (GPU) via a first high-speed interface of the first GPU coupled to a second high-speed interface of a second GPU, a command to provide management data to a baseboard management controller (BMC);

providing, by the first GPU, first management data associated with the first GPU to the second GPU via the first high-speed interface in response to the command;

receiving, by the second GPU, the command;

receiving, by the second GPU, the first management data via the second high-speed interface in response to the command; and

providing, by the second GPU, the first management data and second management data associated with the second GPU to the BMC in further response to the command.

12. The method of claim 11 , wherein the first GPU includes a first management data buffer and the second GPU includes a second management data buffer.

13. The method of claim 12 , further comprising:

storing, by the second GPU, the first management data in a first location of the second management data buffer; and

storing, by the second GPU, the second management data in a second location of the second management data buffer.

14. The method of claim 13 , further comprising:

providing, by the second GPU, the second management data to the first GPU via the second high-speed interface in further response to the command.

15. The method of claim 14 , further comprising:

storing, by the first GPU, the first management data in a first location of the first management data buffer; and

storing, by the first GPU, the second management data in a second location of the first management data buffer.

16. The method of claim 11 , wherein the BMC includes a third high-speed interface coupled to the second high-speed interface.

17. The method of claim 16 , further comprising:

receiving, by the BMC, the first management data and the second management data via the third high-speed interface.

18. The method of claim 11 , wherein the BMC includes a first low-speed interface, the second GPU includes a second low-speed interface coupled to the first low-speed interface, and the first GPU includes a third low-speed interface.

19. The method of claim 18 , further comprising:

receiving, by the first GPU, the command via the third low-speed interface;

receiving, by the second GPU, the command via the second low-speed interface; and

receiving, by the BMC, the first management data and the second management data via the first low-speed interface.

20. An information handling system, comprising:

a first graphics processing unit (GPU) including a first low-speed interface and a first high-speed interface;

a second GPU including a second low-speed interface and a second high-speed interface coupled to the first high-speed interface; and

a baseboard management controller (BMC) including a third low-speed interface coupled to the first and second low-speed interfaces, the BMC configured to:

determine that the BMC cannot communicate with the first GPU via the first low-speed interface; and

provide a command to the second GPU to retrieve management data from the first GPU;

wherein the second GPU is configured to:

request the management data from the first GPU via the second high-speed interface in response to the command;

receive the management data from the first GPU via the second high-speed interface; and

provide the management data to the BMC via the second low-speed interface.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052216/0758) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0680 →
RELEASE OF SECURITY INTEREST AF REEL 052243 FRAME 0773 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0152 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 26, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052243/0773 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 24, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052216/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2020
From: GUPTA, CHITRAK; BISA, RAMA; PATEL, RAJESHKUMAR; PUTHILATHE, CHANDRASEKHAR; PALMER, JOHN; MADDUKURI, AKKIAH; GAVVALA, PAVAN
To: DELL PRODUCTS, LP
Reel/Frame 051468/0543 →