Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion function

1. A method for communication, the method comprising:

in a bank of successive approximation register analog-to-digital converters (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector:

sampling a received analog electrical signal using the DAC controlled by sampling clock pulses; and

converting the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein the converting is initiated using a conversion enable clock pulse generated in a first SAR ADC and wherein if a metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit.

2. The method according to claim 1 , comprising using the sampling clock pulses controlling other of said SAR ADCs to generate metastability flags.

3. The method according to claim 2 , comprising generating a metastability flag when a conversion enable pulse overlaps with a sampling clock pulse.

4. The method according to claim 1 , wherein a sampling clock of a second SAR ADC is used for most significant bit metastability flag generation and is delayed with respect to a sampling clock of the first SAR ADC by one or more clock intervals.

5. The method according to claim 4 , wherein a symbol sampled by the bank of SAR ADCs is successfully converted if a conversion of a least significant bit starts before a next SAR ADC sampling pulse.

6. The method according to claim 1 , wherein if a least significant bit is not converted, a word completion block determines an index of a most significant bit with a metastability flag and compares the index to an index of a last evaluated bit.

7. The method according to claim 6 , wherein:

if the index of the most significant bit with a metastability flag is greater than the index of the last evaluated bit, the word completion block sets all less significant bits to:

complementary values of the most significant bit with a metastability flag if there is no valid data for bits with an index of the most significant bit with a metastability flag; or

a same value as a successfully converted bit with the lowest index if there is valid data for bits with index lower than the most significant bit with a metastability flag.

8. The method according to claim 1 , comprising storing metastability flags in a first SR latch register in the metastability detector.

9. The method according to claim 8 , comprising storing successfully converted bit indicators in a second SR latch register in the metastability detector.

10. The method according to claim 9 , comprising communicating contents of the first and second SR latch registers to a word completion block.

11. A system for communication, the system comprising:

a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector, each of the SAR ADCs being operable to:

sample a received analog electrical signal using the DAC controlled by sampling clock pulses; and

convert the received analog electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit, and wherein if the least significant bit is not converted, the word completion block determines an index of a most significant bit with a metastability flag and compares the index to an index of a last evaluated bit.

12. The system according to claim 11 , wherein the bank of SAR ADCs is operable to initiate the converting using a conversion enable pulse in a first SAR ADC.

13. The system according to claim 12 , wherein the sampling clock pulses controlling other of said SAR ADCs is used to generate metastability flags.

14. The system according to claim 12 , wherein the first SAR ADC is operable to generate a metastability flag when a conversion enable pulse overlaps with a sampling clock pulse.

15. The system according to claim 14 , wherein a sampling clock of a second SAR ADC is used for most significant bit metastability flag generation and is delayed with respect to a sampling clock of the first SAR ADC by one or more clock intervals.

16. The system according to claim 14 , wherein conversion of symbol sampled by the bank of SAR ADCs is successfully converted if the conversion of the least significant bit starts before a next SAR ADC sampling pulse.

17. The system according to claim 11 , wherein:

if the index of the most significant bit with a metastability flag is greater than the index of the last evaluated bit, the word completion block sets all less significant bits to:

complementary values of the most significant bit with a metastability flag if there is no valid data for bits with an index lower than the index of the most significant bit with a metastability flag; or

a same value as a successfully converted bit with the lowest index if there is valid data for bits with index lower than the most significant bit with a metastability flag.

18. The system according to claim 11 , wherein the bank of SAR ADCS is operable to store metastability flags in a first SR latch register in the metastability detector and store successfully converted bit indicators in a second SR latch register in the metastability detector.

19. The system according to claim 18 , wherein the bank of SAR ADCs is operable to communicating contents of the first and second SR latch registers to the word completion block.

20. A system for communication, the system comprising:

a bank of successive approximation register analog-to-digital convertors (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog convertor (DAC), a comparator, and a metastability detector, each of the SAR ADCs being operable to:

sample a received analog electrical signal using the DAC controlled by sampling pulses; and

convert the received analog electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit and sets subsequent bits to complementary values of a most significant bit with a metastability flag or to the same values as the most significant bit with a metastability flag.

21. A system for communication, the system comprising:

a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector, each of the SAR ADCs being operable to:

sample a received analog electrical signal using the DAC controlled by sampling clock pulses; and

convert the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit, and wherein a sampling clock of a first SAR ADC is used for most significant bit metastability flag generation and is delayed with respect to a second SAR ADC sampling clock by one or more clock intervals.

22. A system for communication, the system comprising:

a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector, each of the SAR ADCs being operable to:

sample a received analog electrical signal using the DAC controlled by sampling clock pulses;

convert the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit; and

store metastability flags in a first SR latch register in the metastability detector.

23. A system for communication, the system comprising:

a bank of successive approximation register analog-to-digital converters (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector, each of the SAR ADCs being operable to:

sample a received analog electrical signal using the DAC controlled by sampling clock pulses; and

convert the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein the converting is initiated using a conversion enable clock pulse generated in a first SAR ADC and wherein if a metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit.

24. A method for communication, the method comprising:

in a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector:

sampling a received analog electrical signal using the DAC controlled by sampling clock pulses; and

converting the received analog electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit, and wherein if the least significant bit is not converted, the word completion block determines an index of a most significant bit with a metastability flag and compares the index to an index of a last evaluated bit.

25. A method for communication, the method comprising:

in a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector:

sampling a received analog electrical signal using the DAC controlled by sampling clock pulses; and

converting the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit, and wherein a sampling clock of a first SAR ADC is used for most significant bit metastability flag generation and is delayed with respect to a second SAR ADC sampling clock by one or more clock intervals.

26. A method for communication, the method comprising:

in a bank of successive approximation register analog-to-digital converter (SAR ADCs), each of the SAR ADCs comprising a digital-to-analog converter (DAC), a comparator, and a metastability detector:

sampling a received analog electrical signal using the DAC controlled by sampling clock pulses;

converting the received analog electrical signal to an n-bit digital signal by evaluating bits using the comparator in each of the SAR ADCs, wherein if the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit; and

storing metastability flags in a first SR latch register in the metastability detector.