Frequency management for interference reduction of A/D converters powered by switching power converters

1. A device comprising:

a frequency generator;

a power converter including a first portion and a second portion, wherein the first and second portions are coupled using a first electrical isolation barrier, and the first portion is coupled to the frequency generator;

a clock transmitter coupled to frequency generator;

a clock receiver coupled to the clock transmitter using a second electrical isolation barrier; and

an analog-to-digital converter coupled to the second portion of the power converter and to the clock receiver.

2. The device of claim 1 , wherein the frequency generator includes a phase-locked loop.

3. The device of claim 2 , wherein the phase-locked loop includes:

a phase frequency detector;

a loop filter coupled to the phase frequency detector;

a voltage-controlled oscillator coupled to the loop filter;

a first clock divider coupled between the voltage-controlled oscillator and the phase frequency detector; and

a second clock divider coupled to the voltage-controlled oscillator, wherein the second clock generator is configured to generate a second clock signal provided out of the phase-locked loop, wherein the second clock signal has a frequency that is offset from a frequency of a first clock signal received into the phase-locked loop.

4. The device of claim 1 , wherein the analog-to-digital converter includes a sigma-delta analog-to-digital converter.

5. The device of claim 1 , further comprising an amplifier coupled to the analog-to-digital converter.

6. The device of claim 5 , wherein the amplifier includes a differential instrumentation amplifier.

7. The device of claim 1 , wherein the power converter further includes a transformer coupled between the first and second portions, the transformer providing the first electrical isolation barrier.

8. The device of claim 7 , further comprising an isolation capacitor coupled between the clock transmitter and the clock receiver, the isolation capacitor providing at least a portion of the second electrical isolation barrier.

9. The device of claim 1 , wherein the first portion of the power converter includes a power driver, and the second portion of the power converter includes a rectifier.

10. The device of claim 9 , wherein the second portion of the power amplifier further includes a low-dropout regulator coupled between the rectifier and the analog-to-digital converter.

11. The device of claim 1 , further comprising:

a data transmitter coupled to the analog-to-digital converter; and

a data receiver coupled to the data transmitter using a third electrical isolation barrier.

12. A device comprising:

a first die including:

a frequency generator;

a first portion of a power converter coupled to the frequency generator; and

a clock transmitter coupled to the frequency generator;

a second die including:

a second portion of the power converter coupled to the first portion of the power converter using a first electrical isolation barrier; and

a clock receiver coupled to the clock transmitter using a second electrical isolation barrier; and

an analog-to-digital converter coupled to the second portion of the power converter and to the clock receiver.

13. The device of claim 12 , further comprising a third die that includes the analog-to-digital converter.

14. The device of claim 13 , wherein the third die further includes an amplifier coupled to the analog-to-digital converter.

15. The device of claim 12 , further comprising a transformer coupled between the first and second portions, the transformer providing the first electrical isolation barrier.

16. The device of claim 15 , further comprising a third die that includes the transformer.

17. The device of claim 12 , wherein the first portion of the power converter includes a power driver, and the second portion of the power converter includes:

a rectifier coupled to the power driver using the first electrical isolation barrier; and

a low-dropout regulator coupled between the rectifier and the analog-to-digital converter.

18. The device of claim 12 , further comprising:

a data transmitter on the second die, wherein the data transmitter is coupled to the analog-to-digital converter; and

a data receiver on the first die, wherein the data receiver is coupled to the data transmitter using a third electrical isolation barrier.

19. A method comprising:

receiving a first clock signal having a first frequency;

generating a second clock signal using the first clock signal, wherein the second clock signal has a second frequency that is offset from the first frequency, and the second clock signal is generated on a first side of a first electrical isolation barrier;

generating a power signal using the second clock signal, wherein the power signal is generated on a second side of the first electrical isolation barrier;

powering an analog-to-digital converter using the power signal; and

transmitting the first clock signal to the analog-to-digital converter across a second electrical isolation barrier.

20. The method of claim 19 , wherein powering the analog-to-digital converter using the power signal includes:

rectifying the power signal to generate a rectified signal;

generating a direct current signal using the rectified signal; and

providing the direct current signal to the analog-to-digital converter.

21. The method of claim 19 , further comprising:

generating a third clock signal using the first clock signal; and

transmitting the first clock signal across the second electrical isolation barrier using the third clock signal.

22. The method of claim 19 , further comprising:

receiving data samples from the analog-to-digital converter; and

transmitting the data samples across a third electrical isolation barrier.

23. The method of claim 22 , wherein the data samples are generated by the analog-to-digital converter using the first clock signal.

24. The method of claim 22 , wherein the data samples comprise digital measurements of a voltage across a shunt resistor.

25. The method of claim 19 , wherein a harmonic of the first frequency and a harmonic of the second frequency are separated by a target margin.