Method, apparatus, and electronic device for improving CPU performance
Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.
1. A method comprising:
at each of a plurality of CPU dies of a CPU: enabling threads executing on the CPU die to compete for a respective mutex of the CPU die;
identifying a plurality of threads that have each obtained the respective mutex;
for each remaining thread that has not obtained any respective mutex;
enabling the remaining thread to sleep in order to release an occupied resource of a corresponding CPU die in which the remaining thread is located; and
maintaining a correspondence between the remaining thread and the corresponding CPU die so that the remaining thread resumes competing for the respective mutex of the corresponding CPU die once woken up:
enabling the plurality of threads that have each obtained the respective mutex for a CPU die to compete for a spin lock of the CPU;
identifying, from the plurality of threads, a target thread holding a mutex for a CPU die that has also obtained the spin lock of the CPU;
executing a critical section corresponding to the target thread that has obtained the spin lock; and
releasing the mutex and the spin lock that are obtained by the target thread.
2. The method according to claim 1 , wherein the releasing the mutex and the spin lock that are obtained by the target thread comprises:
first releasing the spin lock obtained by the target thread, and then releasing the mutex obtained by the target thread.
3. The method according to claim 2 , further comprising:
enabling one or more threads that have not obtained the spin lock to continuously detect whether the spin lock is released.
4. The method according to claim 3 , further comprising:
in response to detecting that the spin lock is released, re-competing, by the one or more threads that have not obtained the spin lock, for the spin lock of the CPU.
5. The method according to claim 1 , wherein after the releasing the mutex obtained by the target thread, the method further comprises:
determining whether there is a sleeping thread for the released mutex; and
in response to a positive determining, waking up the sleeping thread, wherein the sleeping thread enters the CPU die corresponding to the released mutex to re-compete for the released mutex.
6. The method according to claim 1 , wherein the mutex of the CPU die is located in a private cache of the CPU.
7. The method according to claim 1 , wherein the mutex comprises a corresponding mutual exclusion lock.
8. The method according to claim 1 , wherein executing the critical section corresponding to the target thread is uninterrupted in a single-core CPU.
9. A non-transitory, computer-readable medium storing one or more instructions executable by a computer system to perform operations comprising:
at each of a plurality of CPU dies of a CPU, enabling threads executing the CPU die to compete for a respective mutex of the CPU die;
identifying a plurality of threads that have each obtained the respective mutex;
for each remaining thread that has not obtained any respective mutex:
enabling the remaining thread to sleep in order to release an occupied resource of a corresponding CPU die in which the remaining thread is located; and
maintaining a correspondence between the remaining thread and the corresponding CPU die so that the remaining thread resumes competing for the respective mutex of the corresponding CPU die once woken up:
enabling the plurality of threads that have obtained the respective mutex to compete for a spin lock of the CPU;
identifying, from the plurality of threads, a target thread holding a mutex for a CPU die that has also obtained the spin lock of the CPU;
executing a critical section corresponding to the target thread that has obtained the spin lock; and
releasing the mutex and the spin lock that are obtained by the target thread.
10. The non-transitory, computer-readable medium according to claim 9 , wherein the releasing the mutex and the spin lock that are obtained by the target thread comprises:
first releasing the spin lock obtained by the target thread, and then releasing the mutex obtained by the target thread.
11. The non-transitory, computer-readable medium according to claim 10 , wherein the operations further comprise:
enabling one or more threads that have not obtained the spin lock to continuously detect whether the spin lock is released.
12. The non-transitory, computer-readable medium according to claim 11 , wherein the operations further comprise:
in response to detecting that the spin lock is released, re-competing, by the one or more threads that have not obtained the spin lock, for the spin lock of the CPU.
13. The non-transitory, computer-readable medium according to claim 9 , wherein after the releasing the mutex obtained by the target thread, the operations further comprise:
determining whether there is a sleeping thread for the released mutex; and
in response to a positive determining, waking up the sleeping thread, wherein the sleeping thread enters the CPU die corresponding to the released mutex to re-compete for the released mutex.
14. The non-transitory, computer-readable medium according to claim 9 , wherein the mutex of the CPU die is located in a private cache of the CPU.
15. The non-transitory, computer-readable medium according to claim 9 , wherein the mutex comprises a corresponding mutual exclusion lock.
16. The non-transitory, computer-readable medium according to claim 9 , wherein executing the critical section corresponding to the target thread is uninterrupted in a single-core CPU.
17. A computer-implemented system, comprising:
one or more computers; and
one or more computer memory devices interoperably coupled with the one or more computers and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more computers, perform one or more operations comprising:
at each of a plurality of CPU dies of a CPU, enabling threads executing on the CPU die to compete for a respective mutex of the CPU die;
identifying a plurality of threads that have each obtained the respective mutex;
for each remaining thread that has not obtained any respective mutex:
enabling the remaining thread to sleep in order to release an occupied resource of a corresponding CPU die in which the remaining thread is located; and
maintaining a correspondence between the remaining thread and the corresponding CPU die so that the remaining thread resumes competing for the respective mutex of the corresponding CPU die once woken up:
enabling the plurality of threads that have each obtained the respective mutex for a CPU die to compete for a spin lock of the CPU;
identifying, from the plurality of threads, a target thread holding a mutex for a CPU die that has also obtained the spin lock of the CPU;
executing a critical section corresponding to the target thread that has obtained the spin lock; and
releasing the mutex and the spin lock that are obtained by the target thread.
18. The computer-implemented system according to claim 17 , wherein the releasing the mutex and the spin lock that are obtained by the target thread comprises:
first releasing the spin lock obtained by the target thread, and then releasing the mutex obtained by the target thread.