Controller with smart scheduling and method of operating the controller

1. A memory system comprising:

a memory controller in communication with a host;

a memory device in communication with the memory controller;

a plurality of queues in the memory controller for holding respective subsets of a plurality of commands with different priorities;

a scheduler in the memory controller configured to schedule the plurality of commands for processing based on respective priorities and expected completion times of the commands for each of the plurality of commands with the different priorities in the queues; and

an error correction decoder in the memory controller operably coupled to the plurality of queues in the memory controller for receiving and decoding the commands according to respective schedules of the commands in the queues waiting for the error correction decoder, as determined by the scheduler,

wherein

in a first queue of the plurality of queues in the memory controller, a first set of commands of the plurality of commands are processed according to que-specific priorities of the first queue and que-specific expected completion times for the memory device to complete the first set of commands including execution latency of the error correction decoder,

the que-specific completion times of the commands in the first queue are based on predicted execution times for the memory device to execute the first set of commands,

predicted wait times for the first set of commands to wait in the first queue are considered by the scheduler,

between queuing the first set of commands in the first queue and sending the first set of commands to the error correction decoder, the scheduler determines an updated priority of a command in the first queue based a current priority, a predicted execution time, and a predicted wait time of the command, and

at each update cycle, the command with highest updated priority is sent to the error correction decoder,

wherein the memory system determines the expected completion times by estimating the execution latency of the error correction decoder, and

wherein the memory system estimates the execution latency of the error correction decoder based on syndrome weight.

2. The memory system of claim 1 , wherein the expected completion time for each of the plurality of commands includes an expected execution time.

3. The memory system of claim 2 , wherein the expected completion time for each of the plurality of commands includes an expected wait time.

4. The memory system of claim 1 , wherein the syndrome weight is based on a parity check matrix of an error correcting code used by the error correction decoder.

5. The memory system of claim 1 , wherein

at each update cycle, a shortest predicted execution time command is placed first in the first queue for the error correction decoder, while a longest predicted execution time command is placed last in the first queue for the error correction decoder.

6. The memory system of claim 1 , wherein the scheduler is configured to schedule the plurality of the commands for processing based on the respective priorities of each of the commands in all of the queues.

7. A method for scheduling and sending commands to an error correction decoder for a memory device, the method comprising:

queueing respective subsets of commands in respective queues;

scheduling the commands for processing by the error correction decoder, using a scheduler, based on respective priorities and expected completion times of the commands for each of the plurality of commands with the different priorities in the queues including execution latency of the error correction decoder;

transmitting the commands from the queues in a memory controller to the error correction decoder for processing according to respective schedules of the commands in the queues waiting for the error correction decoder, as determined in the scheduling operation,

wherein

in a first queue of the respective queues in the memory controller, a first set of commands of the subsets of commands are processed according to que-specific priorities of the first queue and que-specific expected completion times for the memory device to complete the first set of commands,

the que-specific completion times of the commands in the first queue are based on predicted execution times for the memory device to execute the first set of commands,

predicted wait times for the first set of commands to wait in the first queue are considered by the scheduler,

between queuing the first set of commands in the first queue and sending the first set of commands to the error correction decoder, the scheduler determines an updated priority of a command in the first queue based a current priority, a predicted execution time, and a predicted wait time of the command, and

at each update cycle, the command with highest updated priority is sent to the error correction decoder; and

determining the expected completion times of the commands by estimating the execution latency of the error correction decoder,

wherein the scheduling of the commands for processing by the error correction decoder comprises estimating the execution latency of the error correction decoder based on syndrome weight.

8. The method of claim 7 , wherein the expected completion time for each of the plurality of commands includes an expected execution time.

9. The method of claim 8 , wherein the expected completion time of each for the plurality of commands includes an expected wait time.

10. The method of claim 7 , wherein the syndrome weight is based on a parity check matrix of an error correcting code used by the error correction decoder.

11. The method of claim 7 , wherein

at each update cycle, a shortest predicted execution time command is placed first in the first queue for the error correction decoder, while a longest predicted execution time command is placed last in the first queue for the error correction decoder.

12. A memory controller comprising:

a memory controller in communication with a host;

a memory device in communication with the memory controller;

a plurality of queues in the memory controller for holding respective subsets of a plurality of commands with different priorities;

a scheduler in the memory controller to determine or update a priority for each of the commands using a metric function, and to schedule the commands based on the determined or updated priorities of the commands for each of the plurality of commands with the different priorities in the queues; and

an error-correction code (ECC) decoder in the memory controller operably coupled to the plurality of queues in the memory controller for receiving and processing the commands waiting for the ECC decoder according to respective schedules for each command in the queues, as determined by the scheduler,

wherein in a first queue of the plurality of queues in the memory controller, a first set of commands of the plurality of commands are processed according to que-specific priorities of the first queue and que-specific expected completion times for the memory device to complete the first set of commands including execution latency of the ECC decoder,

the que-specific completion times of the commands in the first queue are based on predicted execution times for the memory device to execute the first set of commands,

predicted wait times for the first set of commands to wait in the first queue are considered by the scheduler,

between queuing the first set of commands in the first queue and sending the first set of commands to the ECC decoder, the scheduler determines an updated priority of a command in the first queue based a current priority, a predicted execution time, and a predicted wait time of the command,

at each update cycle, the command with highest updated priority is sent to the ECC decoder,

the expected completion times of the commands are determined by estimating the execution latency of the error correction decoder, and

scheduling of the commands for processing by the error correction decoder comprises estimating the execution latency of the error correction decoder based on syndrome weight.

13. The memory controller of claim 12 , wherein the metric function is selected in accordance with at least one of the following maximize throughput, minimize worst case latency, and improve quality-of-service of the memory controller.

14. The memory controller of claim 12 , further comprising an ECC component in which the plurality of queues, the scheduler and the ECC decoder are embodied.

15. The memory controller of claim 12 , further comprising a control component including a processor, the scheduler being embodied in the control component.