System and method for graphics processing unit firmware updates
An information handling system includes a processor, a graphics processing unit (GPU) including an interrupt interface coupled to the processor, and a low-speed interface, and a baseboard management controller (BMC) coupled to the low-speed interface. The GPU is configured to receive a first command from the BMC via the low-speed interface to halt processing data, to send a first interrupt to the processor via the interrupt interface in response to receiving the first command, to determine that the processor has halted sending data to the first GPU in response to the first interrupt, and to send a first reply to the command in response to determining that the processor has halted sending data. The BMC is configured to reboot the first GPU without rebooting the processor in response to receiving the first reply.
1. An information handling system, comprising:
a processor;
a first graphics processing unit (GPU) including an interrupt interface coupled to the processor, and a low-speed interface; and
a baseboard management controller (BMC) coupled to the low-speed interface;
wherein the first GPU is configured to receive a first command from the BMC via the low-speed interface to halt processing data, to send a first interrupt to the processor via the interrupt interface in response to receiving the first command from the BMC, to determine that the processor has halted sending data to the first GPU in response to sending the first interrupt to the processor, and to send a first reply to the first command from the BMC in response to determining that the processor has halted sending data; and
wherein the BMC is configured to, prior to rebooting the first GPU, send a firmware update to the first GPU in response to receiving the first reply from the first GPU and reboot the first GPU without rebooting the processor in response to receiving the first reply from the first GPU.
2. The information handling system of claim 1 , wherein the processor is further configured to execute the first interrupt to halt data flow to the first GPU.
3. The information handling system of claim 1 , wherein the BMC is further configured to send a second command to the first GPU to resume processing data in response to rebooting the first GPU.
4. The information handling system of claim 3 , wherein the first GPU is further configured to send a second interrupt to the processor in response to receiving the second command from the BMC.
5. The information handling system of claim 4 , wherein the processor is further configured to execute the second interrupt to resume data flow to the first GPU.
6. The information handling system of claim 1 , wherein:
the first GPU further includes a high-speed interface;
the information handling system further comprises a second GPU coupled to the high-speed interface and to the low-speed interface; and
the first GPU is further configured to send the firmware update to the second GPU via the high-speed interface.
7. The information handling system of claim 6 , wherein:
the second GPU is further configured to receive a second command from the BMC via the low-speed interface to halt processing data, to send a third interrupt to the processor via the interrupt interface in response to receiving the second command from the BMC, to determine that the processor has halted sending data to the second GPU in response to sending the third interrupt to the processor, and to send a second reply to the second command from the BMC in response to determining that the processor has halted sending data; and
the BMC is further configured to reboot the second GPU without rebooting the processor in response to receiving the second reply from the second GPU.
8. The information handling system of claim 1 , wherein the low-speed interface comprises an I3C bus.
9. A method, comprising:
coupling a first graphics processing unit (GPU) of an information handling system to a processor of the information handling system via an interrupt interface;
coupling the first GPU to a baseboard management controller (BMC) of the information handling system via a low-speed interface;
receiving, by the first GPU, a first command from the BMC via the low-speed interface to halt processing data;
sending, by the first GPU, a first interrupt to the processor via the interrupt interface in response to receiving the first command from the BMC;
determining, by the first GPU, that the processor has halted sending data to the first GPU in response to sending the first interrupt to the processor;
sending, by the first GPU, a first reply to the first command from the BMC in response to determining that the processor has halted sending data;
prior to rebooting the first GPU, sending, by the BMC, a firmware update to the first GPU in response to receiving the first reply from the first GPU; and
rebooting, by the BMC, the first GPU without rebooting the processor in response to receiving the first reply from the first GPU.
10. The method of claim 9 , further comprising:
executing, by the processor, interrupt code to halt data flow to the first GPU in response to sending the first interrupt to the processor.
11. The method of claim 9 , further comprising:
sending, by the BMC, a second command to the GPU to resume processing data in response to rebooting the first GPU.
12. The method of claim 11 , further comprising:
sending, by the first GPU, a second interrupt to the processor in response to receiving the second command from the BMC.
13. The method of claim 12 , further comprising:
executing, by the processor, interrupt code to resume data flow to the first GPU in response to sending the second interrupt to the processor.
14. The method of claim 9 , wherein:
coupling a second GPU to the first GPU via a high-speed interface; and
sending, by the first GPU, the firmware update to the second GPU via the high-speed interface.
15. The method of claim 14 , further comprising:
receiving, by the second GPU, a second command from the BMC via the low-speed interface to halt processing data;
sending, by the second GPU, a third interrupt to the processor via the interrupt interface in response to receiving the second command from the BMC;
determining, by the second GPU, that the processor has halted sending data to the second GPU in response to sending the third interrupt to the processor;
sending, by the second GPU, a second reply to the second command from the BMC in response to determining that the processor has halted sending data; and
rebooting, by the BMC, the second GPU without rebooting the processor in response to receiving the second reply from the first GPU.
16. The method of claim 9 , wherein the low-speed interface comprises an I3C bus.
17. An information handling system, comprising:
a graphics processing unit (GPU) including a low-speed interface; and
a baseboard management controller (BMC) coupled to the low-speed interface;
wherein the GPU is configured to receive a command from the BMC via the low-speed interface to halt processing data, to send an interrupt via an interrupt interface in response to receiving the command from the BMC, to determine that the GPU has stopped receiving data in response to sending the interrupt, and to send a reply to the command from the BMC in response to determining that the GPU has stopped receiving the data; and
wherein the BMC is configured to, prior to rebooting the GPU, send a firmware update to the GPU in response to receiving the reply from the GPU and reboot the GPU in response to receiving the reply from the GPU.