Parallel scheduling of encryption engines and decryption engines to prevent side channel attacks
This disclosure describes systems on a chip (SOCs) that prevent side channel attacks on encryption and decryption engines of an electronic device. The SoCs of this disclosure concurrently operate key-diverse encryption and decryption datapaths to obfuscate the power trace signature exhibited by the device that includes the SoC. An example SoC includes an encryption engine configured to encrypt transmission (Tx) channel data using an encryption key and a decryption engine configured to decrypt encrypted received (Rx) channel data using a decryption key that is different from the encryption key. The SoC also includes a scheduler configured to establish concurrent data availability between the encryption and decryption engines and activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.
1. A system on a chip (SoC) comprising:
an encryption engine configured to encrypt transmission (Tx) channel data using an encryption key;
a decryption engine configured to decrypt encrypted received (Rx) channel data using a decryption key that is different from the encryption key; and
a scheduler configured to:
establish concurrent data availability with respect to both the encryption engine and the decryption engine; and
based on the concurrent data availability with respect to both the encryption engine and the decryption engine, activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.
2. The SoC of claim 1 , wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance;
based on the encrypted Rx channel data being unavailable to the decryption engine at the first time instance, cause the encryption engine to hold the Tx channel data after the first time instance without encrypting the Tx channel data.
3. The SoC of claim 1 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance; and
based on the encrypted Rx channel data being unavailable to the decryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the decryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the decryption engine to decrypt the decoy traffic; and
activate the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the decoy traffic.
4. The SoC of claim 1 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the encrypted Rx channel data is available to the decryption engine at a first time instance;
determine that the Tx channel data is unavailable to the encryption engine at the first time instance; and
based on the Tx channel data being unavailable to the encryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the encryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the encryption engine to encrypt the decoy traffic; and
activate the decryption engine to decrypt the encrypted Rx channel data concurrently with the encryption engine encrypting the decoy traffic.
5. The SoC of claim 1 , wherein the SoC is integrated into one of a head-mounted device (HMD) of an artificial reality system or a peripheral device of the artificial reality system.
6. The SoC of claim 1 , further comprising a security processor configured to:
select the encryption key based on the Tx channel traffic being associated with a first channel ID; and
select the decryption key that is different from the encryption key based on the encrypted Rx channel traffic being associated with a second channel ID that is different from the first channel ID associated with the Tx channel traffic.
7. The SoC of claim 2 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to determine that the Rx channel data is available to the decryption engine at a second time instance that is subsequent to the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to activate, at substantially the second time instance, the encryption engine to encrypt the held Tx channel data.
8. The SoC of claim 3 , further comprising a direct memory access (DMA) engine configured to discard the decrypted decoy traffic without loading the decrypted decoy traffic to a shared memory (SMEM) coupled to the DMA engine.
9. The SoC of claim 4 , further comprising a direct memory access (DMA) engine configured to discard the encrypted decoy traffic without loading the encrypted decoy traffic to a wireless memory (WMEM) of the SoC.
10. A head-mounted device (HMD) comprising:
an interface; and
a system on a chip (SoC) comprising:
an encryption engine configured to encrypt, for transmission via the interface, transmission (Tx) channel data using an encryption key;
a decryption engine configured to decrypt encrypted received (Rx) channel data received via the interface using a decryption key that is different from the encryption key; and
a scheduler configured to:
establish concurrent data availability with respect to both the encryption engine and the decryption engine; and
based on the concurrent data availability with respect to both the encryption engine and the decryption engine, activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.
11. The HMD of claim 10 , wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance;
based on the encrypted Rx channel data being unavailable to the decryption engine at the first time instance, cause the encryption engine to hold the Tx channel data after the first time instance without encrypting the Tx channel data.
12. The HMD of claim 10 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance; and
based on the encrypted Rx channel data being unavailable to the decryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the decryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the decryption engine to decrypt the decoy traffic; and
activate the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the decoy traffic.
13. The HMD of claim 10 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the encrypted Rx channel data is available to the decryption engine at a first time instance;
determine that the Tx channel data is unavailable to the encryption engine at the first time instance; and
based on the Tx channel data being unavailable to the encryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the encryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the encryption engine to encrypt the decoy traffic; and
activate the decryption engine to decrypt the encrypted Rx channel data concurrently with the encryption engine encrypting the decoy traffic.
14. The HMD of claim 11 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to determine that the Rx channel data is available to the decryption engine at a second time instance that is subsequent to the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is further configured to activate, at substantially the second time instance, the encryption engine to encrypt the held Tx channel data.
15. The HMD of claim 12 , wherein the SoC further comprises a direct memory access (DMA) engine configured to discard the decrypted decoy traffic without loading the decrypted decoy traffic to a shared memory (SMEM) of the HMD.
16. The HMD of claim 13 , further comprising a direct memory access (DMA) engine configured to discard the encrypted decoy traffic without loading the encrypted decoy traffic to a wireless memory (WMEM) of the SoC.
17. A peripheral device comprising:
an interface; and
a system on a chip (SoC) comprising:
an encryption engine configured to encrypt, for transmission via the interface, transmission (Tx) channel data using an encryption key;
a decryption engine configured to decrypt encrypted received (Rx) channel data received via the interface using a decryption key that is different from the encryption key; and
a scheduler configured to:
establish concurrent data availability with respect to both the encryption engine and the decryption engine; and
based on the concurrent data availability with respect to both the encryption engine and the decryption engine, activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.
18. The peripheral device of claim 17 , wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance;
based on the encrypted Rx channel data being unavailable to the decryption engine at the first time instance, cause the encryption engine to hold the Tx channel data after the first time instance without encrypting the Tx channel data.
19. The peripheral device of claim 17 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the Tx channel data is available to the encryption engine at a first time instance;
determine that the encrypted Rx channel data is unavailable to the decryption engine at the first time instance; and
based on the encrypted Rx channel data being unavailable to the decryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the decryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the decryption engine to decrypt the decoy traffic; and
activate the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the decoy traffic.
20. The peripheral device of claim 17 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to:
determine that the encrypted Rx channel data is available to the decryption engine at a first time instance;
determine that the Tx channel data is unavailable to the encryption engine at the first time instance; and
based on the Tx channel data being unavailable to the encryption engine upon a threshold time elapsing after the first time instance, inject decoy traffic into the encryption engine upon the threshold time elapsing after the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to:
activate the encryption engine to encrypt the decoy traffic; and
activate the decryption engine to decrypt the encrypted Rx channel data concurrently with the encryption engine encrypting the decoy traffic.
21. The peripheral device of claim 18 ,
wherein to establish the concurrent data availability with respect to both the encryption engine and the decryption engine, the scheduler is configured to determine that the Rx channel data is available to the decryption engine at a second time instance that is subsequent to the first time instance, and
wherein to activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data, the scheduler is configured to activate, at substantially the second time instance, the encryption engine to encrypt the held Tx channel data.
22. The peripheral device of claim 19 , wherein the SoC further comprises a direct memory access (DMA) engine configured to discard the decrypted decoy traffic without loading the decrypted decoy traffic to a shared memory (SMEM) of the peripheral device.
23. The peripheral device of claim 20 , further comprising a direct memory access (DMA) engine configured to discard the encrypted decoy traffic without loading the encrypted decoy traffic to a wireless memory (WMEM) of the SoC.