IP Library Granted Patent US 11,424,118
Granted Patent B2
US 11,424,118 · App. 16/751,049 · Granted Aug 23, 2022

Electronic devices comprising silicon carbide materials

Inventors: Santanu Sarkar (Boise, ID); Farrell M. Good (Meridian, ID)
Assignee: Micron Technology, Inc.
H01L21/02167C01B32/00C01B33/00C23C16/045C23C16/452H01L21/02274H01L21/02381H01L2221/1047
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Quick Facts
Patent No.
US 11,424,118
App. No.
16/751,049
Granted
Aug 23, 2022
Kind
B2
Abstract

An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Claims (25)

1. An electronic device comprising:

a stack structure comprising one or more stacks of materials, the materials of the one or more stacks comprising a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material; and

one or more silicon carbide materials adjacent to the one or more stacks of materials, the one or more silicon carbide materials comprising silicon carboxide, silicon carbonitride, silicon carboxynitride, or silicon boronitrocarbide, the one or more silicon carbide materials comprising silicon-carbon covalent bonds, and the one or more silicon carbide materials configured as a liner or as a seal.

2. The electronic device of claim 1 , wherein a first silicon carbide material of the one or more silicon carbide materials directly contacts a liner material adjacent to the stacks of materials.

3. The electronic device of claim 1 , wherein a first silicon carbide material of the one or more silicon carbide materials directly contacts sidewalls of the stacks of materials.

4. The electronic device of claim 1 , wherein a second silicon carbide material of the one or more silicon carbide materials directly contacts the first silicon carbide material.

5. The electronic device of claim 1 , wherein a second silicon carbide material of the one or more silicon carbide materials directly contacts a seal material adjacent to the stacks of materials.

6. The electronic device of claim 1 , wherein the one or more silicon carbide materials comprises a carbon content of from about 2 atomic percent (at. %) to about 50 at. % carbon.

7. The electronic device of claim 1 , wherein the one or more silicon carbide materials comprises a homogeneous chemical composition.

8. The electronic device of claim 1 , wherein the one or more silicon carbide materials comprises a gradient of carbon across a thickness of the one or more silicon carbide materials.

9. The electronic device of claim 1 , wherein a chemical composition of the one or more silicon carbide materials configured as a liner comprises a different chemical composition as the one or more silicon carbide materials configured as a seal.

10. The electronic device of claim 1 , wherein a chemical composition of the one or more silicon carbide materials configured as a liner comprises the same chemical composition as the one or more silicon carbide materials configured as a seal.

11. The electronic device of claim 1 , wherein adjacent stacks are spaced at a half pitch of from about 10 nm to about 30 nm.

12. The electronic device of claim 1 , further comprising a fill material in direct contact with the one or more silicon carbide materials.

13. The electronic device of claim 12 , wherein the till material comprises an additional portion of the one or more silicon carbide materials.

14. An electronic device comprising:

an array of memory cells, the memory cells comprising:

stacks of materials comprising a chalcogenide material and one or more additional materials; and

one or more silicon carbide materials adjacent to the stacks of materials, the one or more silicon carbide materials comprising silicon atoms, carbon atoms, and atoms of at least one other chemical element, and the one or more silicon carbide materials comprising silicon-carbon covalent bonds; and

access lines and bit lines electrically coupled to the memory cells.

15. The electronic device of claim 14 , wherein the stacks of materials comprise an aspect ratio of from about 10:1 to about 50:1.

16. The electronic device of claim 14 , wherein the stacks of materials comprise a single chalcogenide material.

17. The electronic device of claim 1 , wherein the chalcogenide material comprises indium.

18. The electronic device of claim 1 , wherein the chalcogenide material comprises germanium.

19. The electronic device of claim 14 , wherein the stacks of materials comprise a single chalcogenide material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2020
From: SARKAR, SANTANU; GOOD, FARRELL M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051603/0772 →
Continuity (1)
Related Publication 20210233768A1 · Jul 29, 2021