IP Library Granted Patent US 10,860,085
Granted Patent B2
US 10,860,085 · App. 16/751,283 · Granted Dec 8, 2020

Modified sleep state graphics processing system

Inventors: Thomas Alexander Shows (Leander, TX); Chung Shou Wu (Taoyuan, TW)
Assignee: Dell Products L.P.
G06F1/3293G06F1/3206G06T1/20Y02D10/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,860,085
App. No.
16/751,283
Granted
Dec 8, 2020
Kind
B2
Abstract

A modified sleep state graphics processing system includes a graphics processing system coupled to a central processing system that is configured to enter different sleep states. A power management engine coupled to the graphics processing system and the central processing system determines that the graphics processing system is operating above a graphics processing activity threshold and, in response, prevents the central processing system from entering a first subset of the different sleep states. The central processing system is configured to communicate with the graphics processing system to cause the graphics processing system to render graphics while prevented from entering the first subset of the different sleep states. The power management engine may then determine that the graphics processing system is operating below the graphics processing activity threshold and, in response, allow the central processing system to enter the first subset of the different sleep states.

Claims (55)

1. A modified sleep state processing system, comprising:

a first processing system;

a second processing system that is coupled to the first processing system, that is configured to communicate with the first processing system to cause the first processing system to perform first processing system operations, and that is configured to enter a plurality of different sleep states; and

a processing system management engine that is coupled to the first processing system and the second processing system, wherein the processing system management engine is configured to:

determine that the first processing system is operating above a processing activity threshold when the first processing system is rendering graphics for a first type application;

prevent, in response to determining that the first processing system is operating above the processing activity threshold, the second processing system from entering a first subset of the plurality of different sleep states;

determine that the first processing system is operating below the processing activity threshold when the first processing system is rendering graphics for a second type application while not rendering graphics for the first type application; and

allow, in response to determining that the first processing system is operating below the processing activity threshold, the second processing system to enter the first subset of the plurality of different sleep states.

2. The system of claim 1 , wherein the processing system management engine is configured to:

detect a connection to an external power supply, wherein the processing system management engine prevents the second processing system from entering the first subset of the plurality of different sleep states in response to determining that the first processing system is operating above the processing activity threshold and detecting the connection to the external power supply.

3. The system of claim 1 , wherein the processing system management engine is configured to:

allow the second processing system to enter a second subset of the plurality of different sleep states while preventing the second processing system from entering the first subset of the plurality of different sleep states; and

cause the second processing system to transition from the second subset of the plurality of different sleep states to an operating state in order to communicate with the first processing system to cause the first processing system to perform the first processing system operations.

4. The system of claim 3 , wherein the second subset of the plurality of different sleep states is a C1 sleep state defined by the Advanced Configuration and Power Interface (ACPI) standard.

5. The system of claim 3 , wherein the second subset of the plurality of different sleep states are associated with a latency variability that is lower than the first subset of the plurality of different sleep states.

6. The system of claim 1 , wherein the determining that the first processing system is operating above the processing activity threshold includes at least one of:

determining that a first processing system temperature of the first processing system is above a temperature threshold;

determining that a first processing system power consumption of the first processing system is above a power consumption threshold; and

determining that a first processing system utilization of the first processing system is above a utilization threshold.

7. The system of claim 1 , wherein the determining that the first processing system is operating above the processing activity threshold includes determining that the first processing system has performed the first processing system operations within a time period, and wherein the determining that the first processing system is operating below the processing activity threshold includes determining that the first processing system has not performed the first processing system operations within the time period.

8. An Information Handling System (IHS), comprising:

a management processing system; and

a management memory system that is coupled to the management processing system and that includes instructions that, when executed by the management processing system, cause the management processing system to:

determine that a first processing system is operating above a processing activity threshold when the first processing system is rendering graphics for a first type application;

prevent, in response to determining that the first processing system is operating above the processing activity threshold, a second processing system from entering a first subset of a plurality of different sleep states;

determine that the first processing system is operating below the processing activity threshold when the first processing system is rendering graphics for a second type application while not rendering graphics for the first type application; and

allow, in response to determining that the first processing system is operating below the processing activity threshold, the second processing system to enter the first subset of the plurality of different sleep states.

9. The IHS of claim 8 , wherein the instructions, when executed by the management processing system, cause the management processing system to:

detect a connection to an external power supply, wherein the management processing system prevents the second processing system from entering the first subset of the plurality of different sleep states in response to determining that the first processing system is operating above the processing activity threshold and detecting the connection to the external power supply.

10. The IHS of claim 8 , wherein the instructions, when executed by the management processing system, cause the management processing system to:

allow the second processing system to enter a second subset of the plurality of different sleep states while preventing the second processing system from entering the first subset of the plurality of different sleep states; and

cause the second processing system to transition from the second subset of the plurality of different sleep states to an operating state in order to communicate with the first processing system to cause the first processing system to perform first processing system operations.

11. The IHS of claim 10 , wherein the second subset of the plurality of different sleep states is a C1 sleep state defined by the Advanced Configuration and Power Interface (ACPI) standard.

12. The IHS of claim 10 , wherein the second subset of the plurality of different sleep states are associated with a latency variability that is lower than the first subset of the plurality of different sleep states.

13. The IHS of claim 8 , wherein the determining that the first processing system is operating above the processing activity threshold includes at least one of:

determining that a first processing system temperature of the first processing system is above a temperature threshold;

determining that a first processing system power consumption of the first processing system is above a power consumption threshold; and

determining that a first processing system utilization of the first processing system is above a utilization threshold.

14. A method for providing modified sleep state processing, comprising:

determining, by a processing system management engine, that a first processing system is operating above a processing activity threshold when the first processing system is rendering graphics for a first type application;

preventing, by the processing system management engine in response to determining that the first processing system is operating above the processing activity threshold, a second processing system from entering a first subset of a plurality of different sleep states;

determining, by the processing system management engine, that the first processing system is operating below the processing activity threshold when the first processing system is rendering graphics for a second type application while not rendering graphics for the first type application; and

allowing, by the processing system management engine in response to determining that the first processing system is operating below the processing activity threshold, the second processing system to enter the first subset of the plurality of different sleep states.

15. The method of claim 14 , further comprising:

detecting, by the processing system management engine, a connection to an external power supply, wherein the preventing the second processing system from entering the first subset of the plurality of different sleep states is performed in response to determining that the first processing system is operating above the processing activity threshold and detecting the connection to the external power supply.

16. The method of claim 14 , further comprising:

allowing, by the processing system management engine, the second processing system to enter a second subset of the plurality of different sleep states while preventing the second processing system from entering the first subset of the plurality of different sleep states; and

causing, by the processing system management engine, the second processing system to transition from the second subset of the plurality of different sleep states to an operating state in order to communicate with the first processing system to cause the first processing system to perform first processing system operations.

17. The method of claim 16 , wherein the second subset of the plurality of different sleep states is a C1 sleep state defined by the Advanced Configuration and Power Interface (ACPI) standard.

18. The method of claim 16 , wherein the second subset of the plurality of different sleep states are associated with a latency variability that is lower than the first subset of the plurality of different sleep states.

19. The method of claim 14 , wherein the determining that the first processing system is operating above the processing activity threshold includes at least one of:

determining that a first processing system temperature of the first processing system is above a temperature threshold;

determining that a first processing system power consumption of the first processing system is above a power consumption threshold; and

determining that a first processing system utilization of the first processing system is above a utilization threshold.

20. The method of claim 14 , wherein the determining that the first processing system is operating above the processing activity threshold includes determining that the first processing system has performed the first processing system operations within a time period, and wherein the determining that the first processing system is operating below the processing activity threshold includes determining that the first processing system has not performed the first processing system operations within the time period.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052216/0758) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0680 →
RELEASE OF SECURITY INTEREST AF REEL 052243 FRAME 0773 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0152 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 26, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052243/0773 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 24, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052216/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: SHOWS, THOMAS ALEXANDER; WU, CHUNG SHOU
To: DELL PRODUCTS L.P.
Reel/Frame 051607/0599 →