Reference voltage circuit and semiconductor device
A reference voltage circuit includes a first MOS transistor pair having a first MOS transistor of an enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to an output terminal; and a second MOS transistor pair having a third MOS transistor of an enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. All the MOS transistors operate in a weak inversion region.
1. A reference voltage circuit, comprising
a first MOS transistor pair;
a second MOS transistor pair; and
an output terminal,
the first MOS transistor pair comprising a first MOS transistor of a first-conductivity enhancement type having a gate and a drain connected to each other; and a second MOS transistor of a first-conductivity depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to the output terminal, and
the second MOS transistor pair comprising a third MOS transistor of the first-conductivity enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor; and a fourth MOS transistor of the first-conductivity depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal,
wherein all of the first MOS transistor to the fourth MOS transistor are configured to operate in a weak inversion region.
2. The reference voltage circuit according to claim 1 , wherein the first MOS transistor pair further comprises additional first-conductivity enhancement type and first-conductivity depletion type MOS transistor pairs.
3. The reference voltage circuit according to claim 1 , further comprising a fifth MOS transistor of the first-conductivity enhancement type having a gate and a drain connected to the source of the first MOS transistor, and a source connected to the gate of the second MOS transistor, the fifth MOS transistor being configured to operate in the weak inversion region.
4. The reference voltage circuit according to claim 1 , further comprising an output circuit inserted between the source of the fourth MOS transistor and the output terminal, the output circuit having a sixth MOS transistor of the first-conductivity depletion type and a seventh MOS transistor of a second-conductivity enhancement type both of which operate in the weak inversion region.
5. The reference voltage circuit according to claim 2 , further comprising an output circuit inserted between the source of the fourth MOS transistor and the output terminal, the output circuit having a sixth MOS transistor of the first-conductivity depletion type and a seventh MOS transistor of a second-conductivity enhancement type both of which operate in the weak inversion region.
6. The reference voltage circuit according to claim 3 , further comprising an output circuit inserted between the source of the fourth MOS transistor and the output terminal, the output circuit having a sixth MOS transistor of the first-conductivity depletion type and a seventh MOS transistor of a second-conductivity enhancement type both of which operate in the weak inversion region.
7. A semiconductor device comprising the reference voltage circuit according to claim 1 .
8. A semiconductor device comprising the reference voltage circuit according to claim 2 .
9. A semiconductor device comprising the reference voltage circuit according to claim 3 .
10. A semiconductor device comprising the reference voltage circuit according to claim 4 .