Circuit arrangement for combined protection of a load from temporary and transient overvoltages
The invention relates to a circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester, in particular a spark gap or a varistor, is provided between network-side input terminals and a second surge arrester, in particular a varistor, is provided between load-side output terminals for follow current limitation. According to the invention, at least one controlled semiconductor switch is provided in each case in the series branch between the input terminal and the output terminal and in the output-side parallel branch, wherein a mechanical switch and a series capacitance are connected in parallel with the semiconductor switch in the series branch. Furthermore, the semiconductor switch in the parallel branch is part of a series circuit comprising a parallel circuit comprising a second surge arrester and a parallel capacitance. A series inductance is provided in the series branch between the input terminal and the parallel circuit comprising the series capacitance, the controlled semiconductor switch and the mechanical switch. A microcontroller for controlling the semiconductor switches is also present, wherein the microcontroller is connected to a current detector in the series branch.
1. A circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester ( 1 ), in particular a spark gap or a varistor, is provided between network-side input terminals (E) and a second surge arrester ( 2 ), in particular a varistor, is provided between load-side output terminals (A) for follow current limitation,
characterized in that
a first controlled semiconductor switch (HLLängs) is provided in the series branch between the input terminal and the output terminal (E; A) and a second controlled semiconductor switch (HLQuer) is provided in an output-side parallel branch, wherein a mechanical switch (S) and a series capacitance (CLängs) are connected in parallel with the first controlled semiconductor switch (HLLängs) in the series branch, furthermore the second controlled semiconductor switch (HLQuer) in the parallel branch is part of a series circuit comprising a parallel circuit of the second surge arrester ( 2 ) and a parallel capacitance (CQuer), with a series inductance (L) in the series branch between the input terminal (E) and the parallel circuit of the series capacitance (CLängs), the first controlled semiconductor switch (HLLängs) and the mechanical switch (S), as well as with a microcontroller (μC) for controlling the first controlled semiconductor switch and the second controlled semiconductor switch, wherein the microcontroller (μC) is connected to a current detector (SD) in the series branch.
2. The circuit arrangement according to claim 1 ,
characterized in that
for overvoltage detection, the microcontroller (μC) is connected to the input terminals (E) so as to receive the respective input voltage value.
3. The circuit arrangement according to claim 1 ,
characterized in that
a device for detecting zero crossing is provided, on the basis of which an in-phase connection of the semiconductor switches may be performed.
4. The circuit arrangement according to claim 1 ,
characterized in that
the control of the first controlled semiconductor switch (HL Längs ) in the series branch is performed via a pulse transformer.
5. The circuit arrangement according to claim 1 ,
characterized in that
when a temporary overvoltage (TOV) is detected, the control of the second controlled semiconductor switch (HL Quer ) in the parallel branch is performed actively by means of a pulse transformer, and when transient overvoltages are detected, the control is performed passively via TOV diodes, wherein the passive control is given as from a voltage which is above the diode voltage.
6. The circuit arrangement according to claim 1 ,
characterized in that
for detecting the output voltage, the microcontroller (μC) is connected to the output terminal (A) so as to provide a logic signal corresponding to the respective load ratio.
7. The circuit arrangement according to claim 1 ,
characterized in that
on the basis of the values obtained by the current detector (SD), an additional connection of the mechanical switch (S) is performed for avoiding the first controlled semiconductor switch in the series branch (HL Längs ) to be overloaded.
8. The circuit arrangement according to claim 1 ,
characterized in that
the series and parallel capacitances (C Längs /C Quer ) form a capacitive voltage divider so as to be able to continue the operation of small loads coupled to the output terminals (A) also in the case of temporary overvoltages (TOV).