IP Library Granted Patent US 11,635,950
Granted Patent B2
US 11,635,950 · App. 16/762,475 · Granted Apr 25, 2023

Arithmetic enhancement of C-like smart contracts for verifiable computation

Inventors: Alexandra Covaci (Canterbury, GB); Simone Madeo (London, GB); Patrick Motylinski (London, GB); Stephane Vincent (Luxembourg, LU)
Assignee: nChain Licensing AG
G06F8/447G06F8/44G06F8/451G06F9/44521G06F16/27G06Q20/401G06Q20/405H04L9/0618H04L9/0637H04L9/0643H04L9/30H04L9/3218H04L9/3236H04L9/3239H04L9/3247H04L9/3263H04L63/12H04L9/3066H04L9/50H04L2209/34H04L2209/56
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,635,950
App. No.
16/762,475
Granted
Apr 25, 2023
Kind
B2
Abstract

A system converts high level source code into an arithmetic circuit that represents the functionality expressed in the source code, such as a smart contract as used in relation to a blockchain platform. The system processes a portion of high level source code to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code.

Claims (34)

1. A computer-implemented method comprising the steps:

processing a portion of source code to generate an arithmetic circuit, including evaluating one or more constants provided in the source code to provide one or more expressions comprising Boolean and/or arithmetic operators, wherein:

the source code is written in a high level programming language and further wherein the source code represents a smart contract; and

the arithmetic circuit comprises one or more arithmetic gates arranged to represent some or all of the functionality expressed in the source code, wherein the arithmetic circuit is a machine executable version of the source code, and is arranged to compute a result.

2. A method according to claim 1 and further comprising the step of:

using the arithmetic circuit to provide a hardware and/or software circuit.

3. A method according to claim 1 wherein:

the arithmetic circuit comprises n-bit wires connected to arithmetic gates.

4. A method according to claim 1 wherein:

the arithmetic circuit is architecture independent.

5. A method according to claim 1 wherein the method further comprises pre-processing of the source code to determine one or more constants, the pre-processing comprising one or more of the following steps:

removing comments;

importing header declarations from header files to source files;

merging multiple source files; and

solving or evaluating directives and macros.

6. A method according to claim 1 wherein the method further comprises the step of detecting all global variables declared in the source code, wherein a global variable relates to a function, a structure or class, a constant and/or an entry point for execution.

7. A method according to claim 1 wherein the method further comprises the step of:

generating a table of symbols to associate each symbol provided in the source code with declaration information provided in the source code, the symbols in the table being global and or local symbols.

8. A method according to claim 1 wherein the method further comprises the step of performing a line-by-line evaluation of the source code which results in an arithmetic and/or logic expression which expresses one or more output variables as a combination of logic and/or arithmetic operations applied on one or more input variables.

9. A method according to claim 8 wherein the line-by-line evaluation of the source code comprises the sub-steps of:

decoding of types;

decoding of expressions;

evaluation of expressions; and/or

allocation of memory for data structures required by said functionality.

10. A method according to claim 8 and further comprising the step of:

mapping the arithmetic and/or logic operations of the expression to arithmetic gates.

11. A method according to claim 10 wherein the mapping step comprises the sub-step of:

performing a wire expansion; and/or performing a wire compression.

12. A method according to claim 1 and further comprising the step:

using the arithmetic circuit to generate a quadratic program comprising a set of polynomials which provide a description of the arithmetic circuit.

13. A method according to claim 12 and further comprising the step:

providing the quadratic program to an entity for execution of the quadratic program using one or more inputs.

14. A computer-implemented system arranged to perform the steps of claim 1 , wherein the system comprises an interpreter arranged to perform the processing of the source code, wherein the interpreter comprises instructions stored in memory and executed by a processor.

15. A non-transitory computer-readable storage medium having stored thereon executable instructions that, as a result of being executed by a processor of a computer system, cause the computer system to at least perform claim 1 .

Assignments (7)
CHANGE OF NAME Recorded Feb 18, 2022
From: NCHAIN HOLDINGS LTD
To: NCHAIN LICENSING AG
Reel/Frame 059193/0946 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053032/0037 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053032/0100 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053032/0115 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053032/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053728/0809 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: COVACI, ALEXANDRA; MADEO, SIMONE; MOTYLINSKI, PATRICK; VINCENT, STEPHANE
To: NCHAIN HOLDINGS LTD
Reel/Frame 053743/0001 →
Priority Claims (6)
GB 1718505 · Nov 9, 2017 · national
GB 1719998 · Nov 30, 2017 · national
GB 1720768 · Dec 13, 2017 · national
GB 1801753 · Feb 2, 2018 · national
GB 1805948 · Apr 10, 2018 · national
GB 1806444 · Apr 20, 2018 · national
Continuity (1)
Related Publication 20200348916A1 · Nov 5, 2020
Cited By (1)
US 12,309,257