IP Library Granted Patent US 11,575,467
Granted Patent B2
US 11,575,467 · App. 16/763,599 · Granted Feb 7, 2023

URLLC transmissions with polar codes

Inventors: Chunxuan Ye (San Diego, CA); Fengjun Xi (San Diego, CA); Kyle Jung-Lin Pan (Saint James, NY)
Assignee: InterDigital Patent Holdings, Inc.
H04L1/0057H04L1/0068H04L1/0071H04L1/1819H04L1/1874H04L29/00
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Quick Facts
Patent No.
US 11,575,467
App. No.
16/763,599
Granted
Feb 7, 2023
Kind
B2
Abstract

Systems, procedures, and instrumentalities are disclosed for transmissions with polar codes. A transmitting entity may determine a mother code length. The mother code length may be based on value(s), e.g., a maximum number of transmissions. The transmitting entity may determine a number of information bits to be polar encoded. The number of information bits may be larger than a number of payload bits. The transmitting entity may map the number of information bits to a number of bit channels of a polar code. The transmitting entity may polar encode the information bits in the bit channels using the determined mother code length. The transmitting entity may partition the polar encoded bits into a number of parts. The number of parts may be based on one or more values, e.g., the maximum number of transmissions. The transmitting entity may transmit bits that have been interleaved to a circular buffer.

Claims (19)

1. A wireless transmit/receive unit (WTRU), comprising:

a processor configured at least in part to:

encode, using a polar coding operation, information bits input to a number of bit channels of a polar coder to obtain encoded bits, wherein the number of bit channels depends at least on a maximum number of transmissions and wherein the polar coding operation uses a mother code length that is based at least on the maximum number of transmissions;

store at least part of the encoded bits in a buffer; and

transmit encoded bits from the buffer.

2. The WTRU of claim 1 , wherein the processor is further configured to partition the encoded bits into a number of parts, wherein the number of parts is a power of two, and wherein the number of parts depends at least on the maximum number of transmissions.

3. The WTRU of claim 2 , wherein the processor is further configured to perform interleaving on at least some of the encoded bits in each part.

4. The WTRU of claim 2 , wherein each respective part of the number of parts corresponds to a respective redundancy version, and wherein the processor is further configured to transmit each respective redundancy version, and wherein each respective redundancy version has a respective starting point in the buffer.

5. The WTRU of claim 2 , wherein the processor is configured to transmit a first portion of the encoded bits stored in the buffer in a first transmission and a second portion of the encoded bits stored in the buffer in a second transmission.

6. The WTRU of claim 1 , wherein the processor is configured to transmit up to the maximum number of transmissions using the encoded bits stored in the buffer during a single polar encoding operation.

7. The method of claim 6 , further comprising performing interleaving on at least some of the encoded bits in each part.

8. The method of claim 6 , wherein each respective part of the number of parts corresponds to a respective redundancy version, and wherein the method further comprises transmitting each respective redundancy version, and wherein each respective redundancy version has a respective starting point in the buffer.

9. A method comprising:

encoding, using a ploar coding operation, information bits input to a number of bit channels of a polar coder, wherein the number of bit channels depends at least on a maximum number of transmissions and wherein the polar coding operation uses a mother code length that is based at least on the maximum number of transmissions;

storing at least part of the encoded bits in a buffer; and

transmitting encoded bits from the buffer.

10. The method of claim 9 , further comprising partitioning the encoded bits into a number of parts, wherein the number of parts is a power of two, and wherein the number of parts depends at least on the maximum number of transmissions.

11. The method of claim 10 , further comprising transmitting a first portion of the encoded bits stored in the buffer in a first transmission and a second portion of the encoded bits stored in the buffer in a second transmission.

12. The method of claim 9 , wherein transmitting of the encoded bits from the buffer includes transmitting up to the maximum number of transmissions using the encoded bits stored in the buffer during a single polar encoding operation.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2023
From: IDAC HOLDINGS, INC.
To: INTERDIGITAL PATENT HOLDINGS, INC.
Reel/Frame 062308/0215 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2022
From: IDAC HOLDINGS, INC.
To: INTERDIGITAL PATENT HOLDINGS, INC.
Reel/Frame 062055/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2022
From: YE, CHUNXUAN; XI, FENGJUN; PAN, KYLE JUNG-LIN
To: IDAC HOLDINGS, INC.
Reel/Frame 059098/0029 →
Continuity (3)
Provisional Application 62630520 · Feb 14, 2018
Provisional Application 62586447 · Nov 15, 2017
Related Publication 20200287659A1 · Sep 10, 2020
Cited By (1)
US 12,342,385