Transistor and method of fabrication of the same including a gate contact formed in a recess through the passivation dielectric layer in contact with the active layer

1. A transistor structure, comprising:

a) a substrate ( 110 , 210 );

b) a piezoelectric active layer ( 112 , 212 ), having a heterojunction, disposed on the substrate ( 110 , 210 );

c) a dielectric passivation layer ( 120 , 220 ) disposed on the active layer ( 112 , 212 ) and having a thickness of between 10 nm and 1000 nm, wherein the passivation layer ( 120 , 220 ) has a recess ( 122 , 222 ) that extends through the entire passivation layer ( 120 , 220 ) in the direction of the active layer ( 112 , 212 ), wherein the recess ( 122 , 222 ) has a width between 10 nm and 500 nm on the boundary to the active layer ( 112 , 212 ) and the ratio between the thickness of the passivation layer ( 120 , 220 ) and the width of the recess ( 122 , 222 ) at the boundary to the active layer ( 112 , 212 ) is between 1.5:1 and 4:1;

d) a gate contact element ( 140 , 240 ) disposed within the recess ( 122 , 222 ), wherein the contact element ( 140 , 240 ) extends from the active layer ( 112 , 212 ) to above the passivation layer ( 120 , 220 ); and

e) a cover layer ( 150 , 250 ) that covers the contact element ( 140 , 240 ) above the passivation layer ( 120 , 220 ); characterized in that

f) at least one layer ( 120 , 220 , 150 , 250 , 230 ) disposed above the active layer ( 112 , 212 ) is tensile stressed or compressively stressed in the area around the contact element ( 140 , 240 ) with a normal tension of |σ|>1 GPa, or the cover layer is tensile stressed in the area around the contact element ( 140 , 240 ) with a normal stress of σ>200 MPa,

g) wherein via the individual stresses in the area around the contact element ( 140 , 240 ), a resulting force on the boundary area between the passivation layer ( 120 , 220 ) and the active layer ( 112 , 212 ) is set, which influences via the piezoelectric effect the electron density in the active layer ( 112 , 212 ) in the area below the contact element ( 140 , 240 ), wherein the normal tensions of stressed layers lie in the range between ±4 GPa.

2. The transistor structure according to the generic term of claim 1 , characterized in that

f) the transistor structure further comprises an intermediate layer ( 230 ), wherein the intermediate layer ( 230 ) is developed between the contact element ( 240 ) and the passivation layer ( 220 );

g) at least one layer ( 120 , 220 , 150 , 250 , 230 ) disposed above the active layer ( 112 , 212 ) is tensile stressed or compressively stressed in the area around the contact element ( 140 , 240 ) with a normal tension of |σ|>200 MPa;

h) wherein via the individual stresses in the area around the contact element ( 140 , 240 ), a resulting force on the boundary area between the passivation layer ( 120 , 220 ) and the active layer ( 112 , 212 ) is set, which influences via the piezoelectric effect the electron density in the active layer ( 112 , 212 ) in the area below the contact element ( 140 , 240 ), wherein the normal tensions of stressed layers lie in the range of between ±4 GPa.

3. An E-transistor ( 200 ) with a transistor structure according to claim 2 , wherein the passivation layer ( 220 ) is developed as a tension-free or moderately compressively or moderately tensile stressed dielectric layer with a normal tension of −1 GPa≤σ≤1 GPa, the intermediate layer ( 230 ) is developed as a highly compressively stressed dielectric layer with a normal tension of σ<−1 GPa, and the cover layer ( 250 ) is developed as a compressively stressed dielectric layer with a normal tension of σ<−200 MPa.

4. A D-transistor with a transistor structure according to claim 2 , wherein the intermediate layer ( 230 ) and the cover layer ( 250 ) are developed as highly tensile stressed dielectric layers with normal tensions of σ>1 GPa, and the passivation layer ( 220 ) is developed as a tension-free or moderately compressively or moderately tensile stressed dielectric layer with a normal tension of 1 GPa≤σ≤1 GPa.

5. An LN-transistor with a gate structure according to claim 2 , wherein the intermediate layer ( 230 ) and the cover layer ( 250 ) are developed as moderately compressively stressed dielectric layers with normal tensions of −1 GPa≤σ<−200 MPa, and the passivation layer ( 220 ) is developed as a tension-free or moderately tensile stressed dielectric layer with a normal tension of 0 GPa≤σ≤1 GPa.

6. The transistor structure according to claim 1 , wherein the passivation layer ( 120 , 220 ) is developed as a highly compressively or tensile stressed dielectric layer with a normal tension of |σ|>1 GPa.

7. An E-transistor ( 100 ) with a transistor structure according to claim 1 , wherein the passivation layer ( 120 ) is developed as a highly compressively stressed dielectric layer with a normal tension of σ<−1 GPa and the cover layer ( 150 ) is developed as a compressively stressed dielectric layer with a normal tension of σ<−200 MPa.

8. A D-transistor with a transistor structure according to claim 1 , wherein the passivation layer ( 120 ) is developed as a moderately tensile stressed dielectric layer with a normal tension of 200 MPa<σ≤1 GPa and the cover layer ( 150 ) is developed as a tensile stressed dielectric layer with a normal tension of σ>200 MPa.

9. A method for producing a transistor structure, comprising the following steps:

a) providing a substrate ( 110 , 210 ) with a piezoelectric active layer ( 112 , 212 ) having a heterojunction disposed on the substrate ( 110 , 210 );

b) applying a dielectric passivation layer ( 120 , 220 ) with a first stress value onto the active layer ( 112 , 212 ), wherein the passivation layer ( 120 , 220 ) has a thickness of between 10 nm and 1000 nm;

c) producing a recess ( 122 , 222 ) in the passivation layer ( 120 , 220 ), wherein the recess ( 122 , 222 ) extends through the entire passivation layer ( 120 , 220 ) in the direction of the active layer ( 112 , 212 ) and on the boundary to the active layer ( 112 , 212 ) has a width of between 10 nm and 500 nm, wherein the ratio between the thickness of the passivation layer ( 120 , 220 ) and the width of the recess ( 122 , 222 ) on the boundary to the active layer ( 112 , 212 ) is between 1.5:1 and 4:1;

d) developing a gate contact element ( 140 , 240 ) disposed within the recess ( 122 , 222 ), wherein the contact element ( 140 , 240 ) extends from the active layer ( 112 , 212 ) to above the passivation layer ( 120 , 220 );

e) applying of a cover layer ( 150 , 250 ) with a second stress value, which covers over the contact element ( 140 , 240 ) above the passivation layer ( 120 , 220 ); characterized in that

f) the development of at least one layer ( 120 , 220 , 150 , 250 ) disposed above the active layer ( 112 , 212 ) is conducted in a tensile stressed or compressively stressed manner in the area around the contact element ( 140 , 240 ) with a normal tension of |σ|>1 GPa, or the development of the cover layer is conducted in a tensile stressed manner with a normal tension of σ>200 MPa, wherein via the individual stresses in the area around the contact element ( 140 , 240 ), a resulting force on the boundary area between the passivation layer ( 120 , 220 ) and the active layer ( 112 , 212 ) is set, which influences via the piezoelectric effect the electron density in the active layer ( 112 , 212 ) in the area below the contact element ( 140 , 240 ), wherein the normal tensions of stressed layers lie in the range between ±4 GPa.

10. A method for producing a gate structure according to the generic term of claim 9 , characterized in that before developing a gate contact element ( 240 ) disposed within the recess ( 222 ), the following further steps are comprised:

c′) applying an intermediate layer ( 230 ) with a third stress within the recess ( 222 ), wherein the intermediate layer ( 230 ) is developed between the contact element ( 240 ) and the passivation layer ( 220 );

c″) producing a second recess ( 232 ) in the intermediate layer ( 230 ), wherein the second recess ( 232 ) extends through the entire intermediate layer ( 230 ) in the direction of the active layer ( 212 );

f) wherein the development of at least one layer ( 120 , 220 , 150 , 250 ) disposed above the active layer ( 112 , 212 ) is conducted in a tensile stressed or compressively stressed manner in the area around the contact element ( 140 , 240 ) with a normal tension of |σ|>200 MPa, wherein via the individual stresses in the area around the contact element ( 140 , 240 ), a resulting force on the boundary area between the passivation layer ( 120 , 220 ) and the active layer ( 112 , 212 ) is set, which influences via the piezoelectric effect the electron density in the active layer ( 112 , 212 ) in the area below the contact element ( 140 , 240 ), wherein the normal tensions of stressed layers lie in the range between ±4 GPa.