Circuit for multiplexing MON pin of receiver optical sub-assembly for optical communication

1. A circuit for multiplexing an MON pin of a receiver optical sub-assembly for optical communication, comprising a receiver optical sub-assembly, a monitoring current receiving component and a control signal input component located outside the receiver optical sub-assembly;

the receiver optical sub-assembly including a trans-impedance amplifier, a photodiode (D 0 ), a first clamping circuit, and a current mirror;

two output terminals of the current mirror being respectively connected to the first clamping circuit so that potentials of the two output terminals of the current mirror are equal; a monitoring current output from the current mirror flowing from a MON pin to the monitoring current receiving component, and being converted into a voltage signal by the monitoring current receiving component and then input into a first analog-to-digital converter to be converted into a digital signal, thereby realizing a current monitoring function;

the control signal input component comprising a second clamping circuit, an output terminal of the second clamping circuit being connected to the MON pin, a voltage Vcont_out of the MON pin being clamped into an input voltage Vcont_in of the second clamping circuit; a voltage comparator or analog-to-digital converter in the receiver optical sub-assembly converting the input voltage Vcont_in into various control variables, thereby controlling the trans-impedance amplifier in the receiver optical sub-assembly;

the input voltage Vcont_in of the second clamping circuit being able to satisfy the first clamping circuit and the second clamping circuit to work normally.

2. The circuit as claimed in claim 1 , wherein the current mirror includes PMOS transistors (M 0 ) and (M 1 ); wherein gates of the PMOS transistors (M 0 ) and (M 1 ) are connected to each other, sources of the PMOS transistors (M 0 ) and (M 1 ) are connected to each other, the source of the PMOS transistor (M 0 ) is connected to a power source voltage Vdd, and a drain of the PMOS transistor (M 0 ) is connected to the gate of the PMOS transistor (M 0 ).

3. The circuit as claimed in claim 2 , wherein the first clamping circuit includes a first error amplifier and a PMOS transistor (M 2 ); wherein drains of the PMOS transistors (MO) and (MI) are connected to positive and negative input terminals of the first error amplifier respectively, wherein the positive input terminal of the first error amplifier is further connected to a cathode of the photodiode (DO); an output terminal of the first error amplifier is connected to a gate of the PMOS transistor (M 2 ); a source of the PMOS transistor (M 2 ) is connected to the drain of the PMOS transistor (MI), and a drain of the PMOS transistor (M 2 ) is connected to the MON pin.

4. The circuit as claimed in claim 3 , wherein the second clamping circuit includes a second error amplifier and a PMOS transistor (M 4 ); wherein a negative input terminal of the second error amplifier is connected to the MON pin, a positive input terminal of the second error amplifier is connected to the input voltage Vcont_in, an output terminal of the second error amplifier is connected to a gate of the PMOS transistor (M 4 ); and a source of the PMOS transistor (M 4 ) is connected to the MON pin.

5. The circuit as claimed in claim 3 , wherein the monitoring current receiving component is an NMOS transistor (M 3 ), a drain of the NMOS transistor (M 3 ) is connected to a drain of the PMOS transistor (M 4 ), a source of the NMOS transistor (M 3 ) is grounded, a gate of the NMOS transistor (M 3 ) is connected to the drain of the NMOS transistor (M 3 ); the gate of the NMOS transistor (M 3 ) is further connected to the first analog-to-digital converter.