Memory system, memory controller and operating method
A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.
1. A memory system comprising:
a memory device comprising a plurality of memory blocks; and
a memory controller configured to control the memory device,
wherein the memory controller determines a time for garbage collection, based on information for a write command group comprising a plurality of write commands inputted from a host, and
wherein the information for the write command group comprises, for each write command included in the write command group, transmission time information indicating a time point at which the host transmits the write command, and write size information indicating a write data size of the write command.
2. The memory system according to claim 1 , wherein the write command group comprises N number of write commands which are most recently transmitted by the host, where N is a natural number.
3. The memory system according to claim 1 , wherein the transmission time information is absolute time information generated by the host.
4. The memory system according to claim 1 , wherein the transmission time information is generated based on a result value obtained by synchronizing relative time information with reference absolute time information generated by the host.
5. The memory system according to claim 1 ,
wherein the information for the write command group is stored in an entry buffer which comprises a plurality of entries, and
wherein each of the plurality of entries comprises transmission time information and write size information for a corresponding write command included in the write command group.
6. The memory system according to claim 5 , wherein the entry buffer is a circular buffer.
7. The memory system according to claim 1 , wherein the time for the garbage collection is determined based on a write data speed that is calculated based on all or a part of the information for the write command group.
8. The memory system according to claim 7 , wherein the faster the write data speed is, the more the time for the garbage collection is reduced.
9. The memory system according to claim 7 , wherein the write data speed is calculated based on a difference between a maximum value and a minimum value of transmission time information included in all or a part of the information for the write command group, and a sum of write data sizes included in all or a part of the information for the write command group.
10. A memory controller comprising:
a memory interface configured to communicate with a memory device comprising a plurality of memory blocks; and
a control circuit configured to control the memory device,
wherein the control circuit determines a time for garbage collection, based on information for a write command group comprising a plurality of write commands inputted from a host, and
wherein the information for the write command group comprises, for each write command included in the write command group, transmission time information indicating a time point at which the host transmits the write command, and write size information indicating a write data size of the write command.
11. The memory controller according to claim 10 , wherein the write command group comprises N number of write commands which are most recently transmitted by the host, where N is a natural number.
12. The memory controller according to claim 10 , wherein the transmission time information is absolute time information generated by the host.
13. The memory controller according to claim 10 , wherein the transmission time information is generated based on a result value obtained by synchronizing relative time information with reference absolute time information generated by the host.
14. The memory controller according to claim 10 ,
wherein the information for the write command group is stored in an entry buffer which comprises a plurality of entries, and
wherein each of the plurality of entries comprises transmission time information and write size information for a corresponding write command included in the write command group.
15. The memory controller according to claim 14 , wherein the entry buffer is a circular buffer.
16. The memory controller according to claim 10 , wherein the time for the garbage collection is determined based on a write data speed that is calculated based on all or a part of the information for the write command group.
17. The memory controller according to claim 16 , wherein the faster the write data speed is, the more the time for the garbage collection is reduced.
18. The memory controller according to claim 16 , wherein the write data speed is calculated based on a difference between a maximum value and a minimum value of transmission time information included in all or a part of the information for the write command group, and a sum of write data sizes included in all or a part of the information for the write command group.
19. A method for operating a memory controller suitable for controlling a memory device, comprising:
receiving a plurality of write commands inputted from a host; and
determining a time for garbage collection, based on information for a write command group comprising a plurality of write commands inputted from the host,
wherein the information for the write command group comprises, for each write command included in the write command group, transmission time information indicating a time point at which the host transmits the write command, and write size information indicating a write data size of the write command.
20. The method according to claim 19 , wherein the write command group comprises N number of write commands which are most recently transmitted by the host, where N is a natural number.