Initialization code/data memory mapping system

1. An initialization code/data memory mapping system, comprising:

at least one memory device storing initialization code and initialization data;

a main memory system; and

a processing system that is coupled to the at least one memory device and the main memory system, wherein the processing system is configured to:

access, via first Memory Mapped Input/Output (MMIO) read operations, the initialization code stored in the at least one memory device that is mapped to an initialization memory space in order to provide an initialization engine;

copy, using the initialization engine, the initialization code from the at least one memory device to the main memory system;

access the initialization code stored in the main memory system in order to provide the initialization engine;

map, using the initialization engine provided via the initialization code stored in the main memory system, the initialization data stored in the at least one memory device to the initialization memory space, wherein the mapping the initialization data stored in the at least one memory device to the initialization memory space hides the initialization code in a runtime environment that is provided following completion of initialization operations by unmapping the initialization code stored in the at least one memory device from the initialization memory space; and

access, via second MMIO read operations, the initialization data stored in the at least one memory device that is mapped to the initialization memory space for use by the initialization engine.

2. The system of claim 1 , wherein the at least one memory device includes a first memory device that stores the initialization code, and a second memory device that stores the initialization data.

3. The system of claim 2 , wherein the first memory device is provided by a Serial Peripheral Interface (SPI) flash memory device, and wherein the second memory device is provided by a second SPI flash memory device.

4. The system of claim 1 , further comprising:

a chipset that is included in the processing system and that has at least one register, wherein the register is configured to store first information to map the initialization code stored in the at least one memory device to the initialization memory space, and second information to map the initialization data stored in the at least one memory device to the initialization memory space.

5. The system of claim 4 , further comprising:

a Central Processing Unit (CPU) that is coupled to the chipset and configured to perform the first MMIO read operations, provide the initialization engine, and perform the second MMIO read operations.

6. An Information Handling System (IHS), comprising:

a processing system that is configured to:

access, via first Memory Mapped Input/Output (MMIO) read operations, initialization code stored in at least one memory device that is mapped to an initialization memory space in order to provide an initialization engine;

copy, using the initialization engine, the initialization code from the at least one memory device to a main memory system;

access the initialization code stored in the main memory system in order to provide the initialization engine;

map, using the initialization engine provided via the initialization code stored in the main memory system, initialization data stored in the at least one memory device to the initialization memory space, wherein the mapping the initialization data stored in the at least one memory device to the initialization memory space hides the initialization code in a runtime environment that is provided following completion of initialization operations by unmapping the initialization code stored in the at least one memory device from the initialization memory space; and

access, via second MMIO read operations, the initialization data stored in the at least one memory device that is mapped to the initialization memory space for use by the initialization engine.

7. The IHS of claim 6 , wherein the at least one memory device includes a first memory device that stores the initialization code, and a second memory device that stores the initialization data.

8. The IHS of claim 7 , wherein the first memory device is provided by a Serial Peripheral Interface (SPI) flash memory device, and wherein the second memory device is provided by a second SPI flash memory device.

9. The IHS of claim 6 , further comprising:

a chipset that is included in the processing system and that has at least one register, wherein the register is configured to store first information to map the initialization code stored in the at least one memory device to the initialization memory space, and second information to map the initialization data stored in the at least one memory device to the initialization memory space.

10. The IHS of claim 9 , further comprising:

a Central Processing Unit (CPU) that is coupled to the chipset and configured to perform the first MMIO read operations, provide the initialization engine, and perform the second MMIO read operations.

11. A method for mapping initialization code memory and initialization data memory, comprising:

accessing, by a processing system via first Memory Mapped Input/Output (MMIO) read operations, initialization code stored in at least one memory device that is mapped to an initialization memory space in order to provide an initialization engine;

copying, by the processing system using the initialization engine, the initialization code from the at least one memory device to a main memory system;

accessing, by the processing system, the initialization code stored in the main memory system in order to provide the initialization engine;

mapping, by the processing system using the initialization engine provided via the initialization code stored in the main memory system, the initialization data stored in the at least one memory device to the initialization memory space, wherein the mapping the initialization data stored in the at least one memory device to the initialization memory space hides the initialization code in a runtime environment that is provided following completion of initialization operations by unmapping the initialization code stored in the at least one memory device from the initialization memory space; and

accessing, by the processing system via second MMIO read operations, the initialization data stored in the at least one memory device that is mapped to the initialization memory space for use by the initialization engine.

12. The method of claim 11 , wherein the at least one memory device includes a first memory device that stores the initialization code, and a second memory device that stores the initialization data.

13. The method of claim 12 , wherein the first memory device is provided by a Serial Peripheral Interface (SPI) flash memory device, and wherein the second memory device is provided by a second SPI flash memory device.

14. The method of claim 11 , further comprising:

storing, in at least one register provided in a chipset that is included in the processing system, first information to map the initialization code stored in the at least one memory device to the initialization memory space; and

storing, in the at least one register provided in the chipset that is included in the processing system, second information to map the initialization data stored in the at least one memory device to the initialization memory space.

15. The method of claim 14 , further comprising:

performing, by a Central Processing Unit (CPU) that is included in the processing system and coupled to the chipset, the first MMIO read operations;

providing, by the CPU, the initialization engine; and

performing, by the CPU, the second MMIO read operations.