IP Library Granted Patent US 11,275,283
Granted Patent B2
US 11,275,283 · App. 16/777,030 · Granted Mar 15, 2022

Display device having a gate lead line

Inventor: Teruhisa Nakagawa (Hyogo, JP)
Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
G02F1/136286G02F1/1368G02F1/134336H01L27/124G02F1/13394G02F1/13452G02F1/13456G02F2201/123G09G2310/021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,275,283
App. No.
16/777,030
Granted
Mar 15, 2022
Kind
B2
Abstract

A display device comprising: a first pixel row including a first pixel electrode and a second pixel electrode arranged in a first direction; a second pixel row including a third pixel electrode and a fourth pixel electrode arranged in the first direction; a third pixel row including a fifth pixel electrode and a sixth pixel electrode arranged in the first direction; a first source line and a second source line extending in the second direction between the first pixel electrode and the second pixel electrode; a first gate line extending in the first direction between the first pixel row and the second pixel row; a second gate line extending in the first direction between the second pixel row and the third pixel row; and a gate lead line extending in the second direction and connected to the first gate line and the second gate line.

Claims (37)

1. A display device comprising:

a first pixel row including a first pixel electrode and a second pixel electrode that are arranged in a first direction;

a second pixel row including a third pixel electrode and a fourth pixel electrode that are arranged in the first direction, the second pixel row being adjacent to the first pixel row in a second direction intersecting the first direction;

a third pixel row including a fifth pixel electrode and a sixth pixel electrode that are arranged in the first direction, the third pixel row being adjacent to the second pixel row in the second direction;

a first source line and a second source line extending in the second direction between the first pixel electrode and the second pixel electrode, between the third pixel electrode and the fourth pixel electrode, and between the fifth pixel electrode and the sixth pixel electrode;

a first gate line extending in the first direction between the first pixel row and the second pixel row;

a second gate line extending in the first direction between the second pixel row and the third pixel row;

a first thin film transistor connected to the first pixel electrode, the first gate line and the first source line;

a second thin film transistor connected to the second pixel electrode, the first gate line and the second source line;

a gate lead line extending in the second direction and connected to the first gate line and the second gate line; and

a spacer disposed on a counter substrate,

wherein the spacer overlaps the first thin film transistor and the second thin film transistor in planar view, and

the gate lead line is disposed between the first source line and the second source line.

2. The display device according to claim 1 ,

wherein the first pixel electrode, the second pixel electrode, the third pixel electrode, the fourth pixel electrode, the fifth pixel electrode, and the sixth pixel electrode have an outer shape with a maximum width in the second direction smaller than a maximum width in the first direction.

3. The display device according to claim 1 , wherein the first pixel electrode includes:

a first area extending at a first angle with respect to the first direction; and

a second area extending at a second angle different from the first angle with respect to the first direction.

4. The display device according to claim 3 , wherein the third pixel electrode includes:

a third area extending at a third angle with respect to the first direction; and

a fourth area extending at a fourth angle different from the third angle with respect to the first direction, and

the boundary between the first area and the second area is arranged in line with a boundary between the third area and the fourth area.

5. The display device according to claim 3 ,

wherein a maximum width in the first direction of the first area is equal to a maximum width in the first direction of the second area.

6. The display device according to claim 1 , wherein

the first source line is disposed closer to the first pixel electrode than the second source line is, and

the second source line is disposed closer to the second pixel electrode than the first source line is.

7. The display device according to claim 1 further comprising a first end connecting wiring that connects the first gate line and the second gate line at an end of the second pixel row.

8. A display device comprising:

a first pixel row including a first pixel electrode and a second pixel electrode that are arranged in a first direction;

a second pixel row including a third pixel electrode and a fourth pixel electrode that are arranged in the first direction, the second pixel row being adjacent to the first pixel row in a second direction intersecting the first direction;

a third pixel row including a fifth pixel electrode and a sixth pixel electrode that are arranged in the first direction, the third pixel row being adjacent to the second pixel row in the second direction;

a first source line and a second source line extending in the second direction between the first pixel electrode and the second pixel electrode, between the third pixel electrode and the fourth pixel electrode, and between the fifth pixel electrode and the sixth pixel electrode;

a first gate line extending in the first direction between the first pixel row and the second pixel row;

a second gate line extending in the first direction between the second pixel row and the third pixel row; and

a gate lead line extending in the second direction and connected to the first gate line and the second gate line,

wherein the gate lead line is disposed between the first source line and the second source line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2020
From: NAKAGAWA, TERUHISA
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 052374/0415 →
Priority Claims (1)
JP JP2019-063282 · Mar 28, 2019 · national
Continuity (1)
Related Publication 20200310208A1 · Oct 1, 2020