IP Library Granted Patent US 11,233,624
Granted Patent B2
US 11,233,624 · App. 16/777,520 · Granted Jan 25, 2022

Cyclic time-slotted operation in a wireless industrial network

Inventors: Zhibo Pang (Västerås, SE); Roger Jansson (Västerås, SE); Michele Luvisotto (Västerås, SE)
Assignee: Hitachi Energy Switzerland AG
H04L5/0082H04W72/0446H04W72/1263H04W84/18H04W88/06
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Quick Facts
Patent No.
US 11,233,624
App. No.
16/777,520
Granted
Jan 25, 2022
Kind
B2
Abstract

A method, a communication device, a computer program, and a computer program product for cyclic time-slotted operation in a wireless industrial network. The communication device includes a memory having a first memory area and a second memory area. The method includes running an application software at application layer. The application software is associated with a first pointer. The method includes operating a communication hardware at physical layer. The communication hardware is associated with a second pointer. The first pointer and the second pointer in a given timeslot point at a respective different one of the memory areas, such that in the given timeslot the application software is enabled to access one of the memory areas and the communication hardware is enabled to access the other of the memory areas. The method includes swapping the pointers to the memory areas at the end of each cycle of the cyclic time-slotted operation.

Claims (43)

1. A method for cyclic time-slotted operation in a wireless industrial network, the method being performed by a communication device, the communication device comprising a memory having a first memory area and a second memory area, each of the first memory area and the second memory area having status fields, the method including:

running an application software at an application layer, the application software being associated with a first pointer;

operating a communication hardware at a physical layer, the communication hardware being associated with a second pointer;

the first pointer and the second pointer in a given timeslot pointing at a respective different one of the memory areas, such that in the given timeslot the application software is enabled to access one of the memory areas and the communication hardware is enabled to access the other of the memory areas;

indicating, in the status field of any timeslot, failure of the communication hardware to transmit or receive a packet in the any timeslot; and

swapping the pointers to the memory areas at an end of each cycle of the cyclic time-slotted operation.

2. The method according to claim 1 , wherein timeslots of each cycle are part of a set of guaranteed timeslots.

3. The method according to claim 2 , wherein each of the first memory area and the second memory area has as many cells for the application software and the communication hardware to access as there are timeslots in the set of guaranteed timeslots.

4. The method according to claim 3 , wherein each set of guaranteed timeslots is part of a superframe.

5. The method according to claim 2 , wherein each set of guaranteed timeslots is part of a superframe.

6. The method according to claim 5 , wherein each cycle has a duration of one superframe, and the pointers are swapped upon start of each superframe.

7. The method according to claim 6 , wherein the application software is cyclically executed, such that one cycle of the application software is executed per superframe.

8. The method according to claim 6 , wherein the superframe further includes a set of shared timeslots.

9. The method according to claim 5 , wherein the application software is cyclically executed, such that one cycle of the application software is executed per superframe.

10. The method according to claim 5 , wherein the superframe further includes a set of shared timeslots.

11. The method according to claim 10 , wherein the shared timeslots are used for handling data that has not been successfully received or transmitted.

12. The method according to claim 1 , wherein each cycle has a duration of one timeslot, and wherein the pointers are swapped upon start of each timeslot.

13. The method according to claim 12 , wherein the application software is cyclically executed, such that the application software is executed once per timeslot.

14. The method according to claim 1 , wherein to access one of the memory areas involves to read from, or write to, said the one of the memory areas.

15. A communication device for cyclic time-slotted operation in a wireless industrial network, the communication device comprising a memory having a first memory area and a second memory area, each of the first memory area and the second memory area having status fields, the communication device further including processing circuitry, the processing circuitry being configured to cause the communication device to:

run an application software at an application layer, wherein the application software is associated with a first pointer;

operate a communication hardware ata physical layer, wherein the communication hardware is associated with a second pointer;

wherein the first pointer and the second pointer in a given timeslot point at a respective different one of the memory areas, such that in the given timeslot the application software is enabled to access one of the memory areas and the communication hardware is enabled to access the other of the memory areas;

indicate, in the status field of any timeslot, failure of the communication hardware to transmit or receive a packet in the any timeslot; and

swap the pointers to the memory areas at an end of each cycle of the cyclic time-slotted operation.

16. A communication device for cyclic time-slotted operation in a wireless industrial network, the communication device comprising:

a memory having a first memory area and a second memory area, each of the first memory area and the second memory area having status fields;

a non-transitory computer readable storage medium comprising computer code; and

processing circuitry in communication with the storage medium, wherein the processing circuitry executes the computer code to:

run an application software at an application layer, wherein the application software is associated with a first pointer;

operate a communication hardware at a physical layer, wherein the communication hardware is associated with a second pointer;

wherein the first pointer and the second pointer in a given timeslot point at a respective different one of the memory areas, such that in the given timeslot the application software is enabled to access one of the memory areas and the communication hardware is enabled to access the other of the memory areas;

indicate, in the status field of any timeslot, failure of the communication hardware to transmit or receive a packet in the any timeslot; and

swap the pointers to the memory areas at an end of each cycle of the cyclic time-slotted operation.

17. The communication device according to claim 16 , wherein timeslots of each cycle are part of a set of guaranteed timeslots.

18. The communication device according to claim 17 , wherein each of the first memory area and the second memory area has as many cells for the application software and the communication hardware to access as there are timeslots in the set of guaranteed timeslots.

19. The communication device according to claim 17 , wherein each set of guaranteed timeslots is part of a superframe.

20. A computer program product for cyclic time-slotted operation in a wireless industrial network, the computer program product comprising a non-transitory computer readable storage medium and a computer program stored on the non-transitory computer readable storage medium, the computer program comprising computer code which, when run on processing circuitry of a communication device including a memory having a first memory area and a second memory area, each of the first memory area and the second memory area having status fields, causes the communication device to:

run an application software at an application layer, wherein the application software is associated with a first pointer;

operate a communication hardware at a physical layer, wherein the communication hardware is associated with a second pointer;

wherein the first pointer and the second pointer in a given timeslot point at a respective different one of the memory areas, such that in the given timeslot the application software is enabled to access one of the memory areas and the communication hardware is enabled to access the other of the memory areas;

indicate, in the status field of any timeslot, failure of the communication hardware to transmit or receive a packet in the any timeslot; and

swap the pointers to the memory areas at an end of each cycle of the cyclic time- slotted operation.

Assignments (5)
MERGER Recorded Nov 13, 2023
From: HITACHI ENERGY SWITZERLAND AG
To: HITACHI ENERGY LTD
Reel/Frame 065548/0905 →
CHANGE OF NAME Recorded Dec 31, 2021
From: ABB POWER GRIDS SWITZERLAND AG
To: HITACHI ENERGY SWITZERLAND AG
Reel/Frame 058601/0692 →
CHANGE OF NAME Recorded Dec 9, 2021
From: ABB POWER GRIDS SWITZERLAND AG
To: HITACHI ENERGY SWITZERLAND AG
Reel/Frame 058548/0306 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2021
From: ABB SCHWEIZ AG
To: ABB POWER GRIDS SWITZERLAND AG
Reel/Frame 055589/0769 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: PANG, ZHIBO; JANSSON, ROGER; LUVISOTTO, MICHELE
To: ABB SCHWEIZ AG
Reel/Frame 052204/0935 →