Network systems and methods for CXL standard
A first processing unit for a computer server apparatus includes a first circuit configured to process a first type of data to be transmitted and received over a communication channel in accordance with a peripheral component interconnect express (PCIe) protocol, a second circuit configured to process a second type of data to be transmitted and received over the communication channel in accordance with a compute express link (CXL) protocol, and an optical communication interface configured to modulate the first type of data and the second type of data into a first signal in a PAM format to be transmitted over the communication channel to a second processing unit and receive, from the second processing unit over the communication channel, a second signal including either one of the first type of data and the second type of data modulated in the PAM format.
1. A first processing unit for a computer server apparatus, the first processing unit comprising:
a first circuit configured to process a first type of data to be transmitted and received over a communication channel in accordance with a peripheral component interconnect express (PCIe) protocol;
a second circuit configured to process a second type of data to be transmitted and received over the communication channel in accordance with a compute express link (CXL) protocol; and
an optical communication interface configured to (i) modulate the first type of data and the second type of data into a first signal in a PAM format to be transmitted over the communication channel to a second processing unit and (ii) receive, from the second processing unit over the communication channel, a second signal including either one of the first type of data and the second type of data modulated in the PAM format.
2. The first processing unit of claim 1 , further comprising a forward error correction module configured to perform forward error correction on at least one of the first type of data and the second type of data.
3. The first processing unit of claim 1 , further comprising a clock data recovery module configured to recover a clock signal from the second signal received over the communication channel.
4. The first processing unit of claim 1 , further comprising a silicon photonic module configured to modulate each of the first type of data and the second type of data into the first signal to be transmitted over the communication channel.
5. The first processing unit of claim 1 , further comprising a wavelength division multiplexing module configured to perform wavelength multiplexing on the first type of data and the second type of data to be transmitted over the communication channel in the first signal.
6. The first processing unit of claim 1 , the optical communication interface being configured to transmit and receive signals in the PAM format (i) at a coding gain between 3 dB and 20 dB and (ii) at a forward error correction latency between 20 and 300 nanoseconds.
7. The first processing unit of claim 2 , the optical communication interface being configured to transmit the first signal and receive the second signal over the communication channel at between 16 Gigabits and 256 Gigabits per second.
8. The first processing unit of claim 1 , the second circuit being configured to (i) select a process from among a cache process, a memory process, and an I/O process and (ii) process and the second type of data in accordance with the selected process.
9. The first processing unit of claim 1 , further comprising a non-return to zero (NRZ) circuit configured to generate configuration data to be transmitted over an NRZ link of the communication channel.
10. A system comprising the first processing unit of claim 1 and further comprising:
the communication channel; and
the second processing unit,
the second processing unit corresponding to at least one of (i) a memory device, (ii) a processing device, and (iii) a network interface coupled to the communication channel.
11. The system of claim 10 , the processing device being one of a digital signal processing device and an artificial intelligence processing device.
12. The system of claim 10 , the memory device being a non-volatile memory device.
13. The system of claim 12 , the non-volatile memory device being one of a dynamic random access memory device, a static random access memory device, a Flash memory device, and a fixed memory device.
14. A system comprising the first processing unit of claim 1 and further comprising:
the communication channel; and
a retimer device coupled to the first processing unit and the communication channel.
15. The system of claim 14 , wherein the retimer device is configured to receive data at a first rate and transmit data at a second rate greater than the first rate.
16. The system of claim 14 , the retimer device comprising (i) a first interface configured to receive the first type data and the second type of data from the first processing unit in the PAM format and (ii) a second interface configured to transmit the first type of data and the second type of data to the first processing unit in the PAM format.
17. The system of claim 16 , each of the first interface and the second interface comprising a plurality of communication lanes configured to transmit data in both the PAM format and a non-return to zero (NRZ) format.
18. The system of claim 17 , the retimer device further comprising a (i) a third interface configured to receive the first type of data and the second type of data from the communication channel in either of the PAM format and the NRZ format and (ii) a fourth interface configured to transmit the first type of data and the second type of data to the communication channel in either of the PAM format and the NRZ format.