Memory system for write operation and method thereof
A memory system includes a memory device and a controller. The controller receives data from a host, allocates buffers after a throttling delay, buffers the data in the buffers, provides the buffered data to the memory device for a write operation, generates a response associated with the write operation, and transmits the response to the host. The controller inserts a throttling delay before allocating the buffers and/or transmitting the response. The throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data. The throttling delay is corrected based on the difference of the number of currently allocated buffers and a buffer reserve threshold.
1. A memory system comprising:
a memory device; and
a controller suitable for:
receiving data from a host;
allocating buffers;
buffering the data in the buffers;
providing the buffered data to the memory device for a write operation;
generating a response associated with the write operation; and
transmitting the response to the host,
wherein the controller performs one of the allocating and the transmitting after a throttling delay, and
wherein the throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data.
2. The memory system of claim 1 , wherein the controller flushes, to the memory device, a fixed amount of the buffered data per flush.
3. The memory system of claim 2 , wherein the throttling delay is determined based on average flush period, the fixed amount of flushed data and a transfer time of the data from the host.
4. The memory system of claim 3 , wherein the throttling delay is corrected such that the number of currently allocated buffers is kept within a particular range.
5. A method for operating a memory system comprising:
receiving data from a host;
allocating buffers after a throttling delay;
buffering the data in the buffers;
providing the buffered data to a memory device for a write operation;
generating a response associated with the write operation; and
transmitting the response to the host,
wherein the throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data.
6. The method of claim 5 , wherein the providing of the buffered data includes flushing, to the memory device, a fixed amount of the buffered data per flush.
7. The method of claim 6 , wherein the throttling delay is determined based on average flush period, the fixed amount of flushed data and a transfer time of the data from the host.
8. The method of claim 7 , wherein the throttling delay is corrected such that the number of currently allocated buffers is kept within a particular range.
9. A method for operating a memory system comprising:
receiving data from a host;
allocating buffers;
buffering the data in the buffers;
providing the buffered data to a memory device for a write operation;
generating a response associated with the write operation; and
transmitting, to the host, the response after a throttling delay,
wherein the throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data.
10. The method of claim 9 , wherein the providing of the buffered data includes flushing, to the memory device, a fixed amount of the buffered data per flush.
11. The method of claim 10 , wherein the throttling delay is determined based on average flush period, the fixed amount of data and a transfer time of the data from the host.
12. The method of claim 11 , wherein the throttling delay is corrected such that the number of currently allocated buffers is kept within a particular range.