IP Library Granted Patent US 11,048,638
Granted Patent B1
US 11,048,638 · App. 16/779,727 · Granted Jun 29, 2021

Host cache-slot aware 10 management

Inventors: Jack Fu (Brighton, MA); Jaeyoo Jung (Shrewsbury, MA); Arieh Don (Newton, MA)
Assignee: EMC IP Holding Company LLC
G06F12/0888G06F3/0604G06F3/067G06F3/0635G06F12/084G06F12/0875G06F2212/452G06F2212/621
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Quick Facts
Patent No.
US 11,048,638
App. No.
16/779,727
Granted
Jun 29, 2021
Kind
B1
Abstract

A host system may be cache-slot aware such that the host system can distribute IOs to processing nodes on a storage system according to cache slot boundaries. A multi-path driver of the host system may determine the cache slot size from one or more communications exchanged with the storage system. The multi-path driver may transition between processing nodes according to slot cache slot boundaries. For IO operations having data portions smaller than the cache slot size, the MP driver may direct multiple IO operations to a same processing node until the collective size of data portions fills a cache slot. For IO operations having a data portion larger than the cache slot, the MP driver may divide the IO operation into sequential IO operations having data portions of a same size as a cache slot, and may transition between processing nodes for each IO operation or a multiple thereof.

Claims (70)

1. For a storage network including a storage system having a plurality of physical storage devices for storing data and a memory cache including a plurality of cache slots, and a host system having an application executing thereon that results in input/output (IO) operations being sent to the storage system, a method performed on the host system comprising:

accessing an IO operation received from the application executing on the host system;

determining that the IO operation is a sequential IO operation;

determining whether a data portion of the IO operation would fit in a current cache slot of the plurality of cache slots currently being used for IO operations of the application; and

selecting an IO path between the host system and the storage system for the IO operation based at least in part on the determination of whether a data portion would fit in the current cache slot.

2. The method of claim 1 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots, the method further comprising:

determining a predefined number of cache slots to be consumed on a processing node for sequential IO operations before transitioning to a next processing node,

wherein the IO path is selected based at least in part on the predefined number of cache slots.

3. The method of claim 2 , wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would not fit in the current cache slot of the plurality of cache slots, and

wherein selecting the IO path includes selecting, based at least in part on the predefined number and the determination that the data portion would not fit in the current cache slot, an IO path corresponding to a next processing node of the plurality of processing nodes in a predefined order of the plurality or processing nodes.

4. The method of claim 2 , wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would not fit in the current cache slot of the plurality of cache slots, and

wherein selecting the IO path includes selecting, based at least in part on the predefined number and the determination that the data portion would not fit in the current cache slot, an IO path corresponding to the current processing node.

5. The method of claim 1 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots,

wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would fit in the current cache slot of the plurality of cache slots, and

wherein, based at least in part on the determination that the data portion would fit in the current cache slot, the selected IO path is an IO path corresponding to the current processing node.

6. The method of claim 1 , wherein each of the plurality of cache slots has a predefined size, and wherein the method further comprises:

determining that a size of the data portion is larger than the predetermined size; and

dividing the IO operation into multiple IO operation according to the predefined size.

7. The method of claim 1 , further comprising:

tagging an IO communication including the IO operation with an indication that the IO operation is a sequential IO operation; and

sending the IO communication along the selected IO path to the storage system.

8. A host system for a storage network including a storage system having a plurality of physical storage devices for storing data and a memory cache including a plurality of cache slots, and the host system, the host system comprising:

an application executing on the host system resulting in input/output (IO) operations being sent to the storage system; and

a memory having code thereon that, when executed, performs a method including:

accessing an IO operation received from the application executing on the host system;

determining that the IO operation is a sequential IO operation;

determining whether a data portion of the IO operation would fit in a current cache slot of the plurality of cache slots currently being used for IO operations of the application; and

selecting an IO path between the host system and the storage system for the IO operation based at least in part on the determination of whether a data portion would fit in the current cache slot.

9. The host system of claim 8 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots, and

wherein the method further includes determining a predefined number of cache slots to be consumed on a processing node for sequential IO operations before transitioning to a next processing node, wherein the IO path is selected based at least in part on the predefined number of cache slots.

10. The host system of claim 9 , wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would not fit in the current cache slot of the plurality of cache slots, and

wherein selecting the IO path includes selecting, based at least in part on the predefined number and the determination that the data portion would not fit in the current cache slot, an IO path corresponding to a next processing node of the plurality of processing nodes in a predefined order of the plurality or processing nodes.

11. The host system of claim 9 , wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would not fit in the current cache slot of the plurality of cache slots, and

wherein selecting the IO path includes selecting, based at least in part on the predefined number and the determination that the data portion would not fit in the current cache slot, an IO path corresponding to the current processing node.

12. The host system of claim 8 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots,

wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would fit in the current cache slot of the plurality of cache slots, and

wherein, based at least in part on the determination that the data portion would fit in the current cache slot, the selected IO path is an IO path corresponding to the current processing node.

13. The host system of claim 8 , wherein each of the plurality of cache slots has a predefined size, and wherein the method further includes:

determining that a size of the data portion is larger than the predetermined size; and

dividing the IO operation into multiple IO operation according to the predefined size.

14. The host system of claim 8 , wherein the method further includes:

tagging an IO communication including the IO operation with an indication that the IO operation is a sequential IO operation; and

sending the IO communication along the selected IO path to the storage system.

15. For a storage network including a storage system having a plurality of physical storage devices for storing data and a memory cache including a plurality of cache slots, and a host system having an application executing thereon that results in input/output (IO) operations being sent to the storage system and having a computer-readable media having software stored thereon, the software comprising:

executable code that accesses an IO operation received from the application executing on the host system;

executable code that determines that the IO operation is a sequential IO operation;

executable code that determines whether a data portion of the IO operation would fit in a current cache slot of the plurality of cache slots currently being used for IO operations of the application; and

executable code that selects an IO path between the host system and the storage system for the IO operation based at least in part on the determination of whether a data portion would fit in the current cache slot.

16. The computer-readable media of claim 15 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots, the software further comprising:

executable code that determines a predefined number of cache slots to be consumed on a processing node for sequential IO operations before transitioning to a next processing node,

wherein the IO path is selected based at least in part on the predefined number of cache slots.

17. The computer-readable media of claim 16 , wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would not fit in the current cache slot of the plurality of cache slots, and

wherein selecting the IO path includes selecting, based at least in part on the predefined number and the determination that the data portion would not fit in the current cache slot, an IO path corresponding to a next processing node of the plurality of processing nodes in a predefined order of the plurality or processing nodes.

18. The computer-readable media of claim 15 , wherein the storage system further includes a plurality of physically discrete storage processing nodes, each storage processing node including a compute component for executing logic to process IO operations and a memory, the memory including a cache segment for use as part of a shared cache distributed across the plurality of processing nodes, wherein the shared cache includes the plurality of cache slots,

wherein the current cache slot is on a current processing node of the plurality of processing nodes,

wherein it is determined that the data portion of the IO operation would fit in the current cache slot of the plurality of cache slots, and

wherein, based at least in part on the determination that the data portion would fit in the current cache slot, the selected IO path is an IO path corresponding to the current processing node.

19. The computer-readable media of claim 15 , wherein each of the plurality of cache slots has a predefined size, and wherein the software further comprises:

executable code that determines that a size of the data portion is larger than the predetermined size; and

executable code that divides the IO operation into multiple IO operation according to the predefined size.

20. The computer-readable media of claim 15 , wherein the software further comprises:

executable code that tags an IO communication including the IO operation with an indication that the IO operation is a sequential IO operation; and

executable code that sends the IO communication along the selected IO path to the storage system.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: FU, JACK; JUNG, JAEYOO; DON, ARIEH
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 051696/0806 →