In-rush current protected power converter
Circuits and methods for protecting the switches of charge pump-based power converters from damage if a V OUT short circuit event occurs and/or if V IN falls rapidly with respect to V X or V OUT . A general embodiment includes a V X Detection Block coupled to the core block of a power converter. The V X Detection Block is coupled to V X and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in V X during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a V IN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of V IN to the power converter. The V IN Detection Block is coupled to V IN , and to V X or V OUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
1. A power converter including:
(a) a converter circuit configured to convert and input voltage V IN to a different output voltage V OUT ;
(b) a control block for disabling operation of the converter circuit;
(c) a voltage node V X between the converter circuit and the output V OUT ;
(d) a V X detection block, coupled to the voltage node V X and to the control block, and configured to detect a voltage drop at the voltage node V X and generate a control signal to the control block to disable operation of the converter circuit;
wherein the converter circuit is coupled to a source of non-overlapping clock signals having ON states separated by a dead time, and wherein the V X detection block is configured to detect the voltage drop at the voltage node V X during the dead time.
2. The invention of claim 1 , wherein the V X detection block is configured to detect a voltage drop at the voltage node V X where the voltage drop has a magnitude that induces damage to the converter circuit.
3. The invention of claim 1 , wherein the control block is configured to interrupt the clock signals within the dead time if the V X detection block detects the voltage drop at the voltage node V X during the dead time.
4. The invention of claim 1 , wherein the dead time is less than about 50 nsec.
5. The invention of claim 1 , wherein the converter circuit, the control block, the voltage node V X , and the V X detection block are embodied in a single integrated circuit die.
6. The invention of claim 1 , wherein the V X detection block includes a sample-and-hold circuit and comparator circuit configured to compare a first voltage at the voltage node V X against a second voltage at the voltage node V X .
7. The invention of claim 1 , wherein the V X detection block includes:
(a) a PMOS FET having a gate coupled to the voltage node V X , a source, and a drain;
(b) a resistor coupled between the voltage node V X and the source of the PMOS FET;
(c) a capacitor coupled between the source of the PMOS FET and a reference voltage;
(d) an inverter coupled to the drain of the PMOS FET; and
(e) a threshold voltage adjustment circuit coupled to the drain of the PMOS FET;
wherein the PMOS FET causes the inverter to generate the control signal if a voltage applied to the gate of the PMOS FET from the voltage node V X has a voltage drop relative to a voltage across the capacitor.
8. The invention of claim 7 , further including a degeneration resistor coupled between the capacitor and the source of the PMOS FET.
9. The invention of claim 1 , wherein the V X detection block includes:
(a) a PMOS FET having a gate coupled to the voltage node V X , a source, and a drain;
(b) a sample-and-hold circuit coupled between the voltage node V X and the source of the PMOS FET, and configured to hold a first voltage occurring at the voltage node V X ;
(c) an inverter coupled to the drain of the PMOS FET; and
(d) a threshold voltage adjustment circuit coupled to the drain of the PMOS FET;
wherein the PMOS FET causes the inverter to generate the control signal if a second voltage applied to the gate of the PMOS FET from the voltage node V X has a voltage drop relative to the first voltage held by the sample-and-hold circuit.
10. The invention of claim 9 , further including a degeneration resistor coupled between the sample-and-hold circuit and the source of the PMOS FET.
11. A power converter including:
(a) a converter circuit configured to convert and input voltage V IN to a different output voltage V OUT ;
(b) a control block for disabling operation of the converter circuit;
(c) a voltage node V X between the converter circuit and the output V OUT ;
(d) a V X detection block, coupled to the voltage node V X and to the control block, and configured to detect a voltage drop at the voltage node V X and generate a control signal to the control block to disable operation of the converter circuit, wherein the V X detection block includes;
(1) a sample-and-hold circuit coupled to the voltage node V X and configured to hold a first voltage occurring at the voltage node V X ;
(2) a comparator circuit, coupled to the voltage node V X and to the sample-and-hold circuit, and configured to compare the first voltage to a second voltage at the voltage node V X .
12. A method for protecting a power converter, including:
(a) monitoring, during a dead time between non-overlapping clock signals controlling operation of the converter circuit, a voltage node V X of a converter circuit of the power converter for a voltage drop; and
(b) disabling operation of the converter circuit upon detection of the voltage drop at the voltage node V X .
13. The method of claim 12 , wherein the voltage drop at the voltage node V X has a magnitude that induces damage to the power converter.