Drive circuit, display device, and drive method
View Patent ↗A drive circuit includes an output circuit provided in a display panel to output a gate-on voltage and a gate-off voltage to a plurality of gate lines. The plurality of gate lines include first to sixth gate lines sequentially disposed in a scanning direction. A first transistor is put into an on state to electrically connect the first gate line and the third gate line, a second transistor is put into the on state to electrically connect the second gate line and the fourth gate line, the third transistor is put into the on state to electrically connect the third gate line and the fifth gate line, and the fourth transistor is put into the on state to electrically connect the fourth gate line and the sixth gate line, after the output circuit outputs the gate-on voltage to the first to fourth gate line.
1. A drive circuit comprising:
a first output circuit that outputs a gate-on voltage and a gate-off voltage to a first gate line;
a second output circuit that outputs the gate-on voltage and the gate-off voltage to a second gate line disposed in a scanning direction with respect to the first gate line;
a first transistor in which one of conductive electrodes is electrically connected to the first gate line;
a second transistor in which one of conductive electrodes is electrically connected to the second gate line;
a connection wiring in which another conductive electrode of the first transistor and another conductive electrode of the second transistor are electrically connected to each other,
wherein the first transistor and the second transistor are put into an on state to electrically connect the first gate line and the second gate line through the connection wiring after the first output circuit outputs the gate-on voltage to the first gate line; and
a control transistor in which one of conductive electrodes is connected to the second output circuit while another conductive electrode is connected to a control electrode of the first transistor and a control electrode of the second transistor, the control electrodes being connected to a control line through which a control signal is supplied,
wherein after the first output circuit outputs the gate-on voltage to the first gate line, the control signal is supplied to the control line and the control transistor is put into an on state to put the first transistor and the second transistor into the on state so as to electrically connect the first gate line and the second gate line through the connection wiring.
2. The drive circuit according to claim 1 , wherein
the first transistor and the second transistor are disposed between the first gate line and the second gate line, the first gate line and the second gate line being adjacent to each other in the scanning direction, and
the first gate line and the second gate line are electrically connected to each other through the connection wiring when the first transistor and the second transistor are in the on state.
3. The drive circuit according to claim 1 , wherein the control transistor is put into the on state to electrically connect the first gate line and the second gate line through the connection wiring when the first output circuit outputs the gate-on voltage to the first gate line.
4. The drive circuit according to claim 1 , wherein the control transistor is put into the on state to electrically connect the first gate line and the second gate line through the connection wiring before the second output circuit outputs the gate-on voltage to the second gate line.
5. The drive circuit according to claim 1 , wherein the control transistor is put into the on state to electrically connect the first gate line and the second gate line through the connection wiring when the first gate line and the second gate line are in a floating state.
6. The drive circuit according to claim 1 , wherein the control transistor is put into the on state to distribute part of a charge charged in the first gate line to the second gate line.
7. The drive circuit according to claim 1 , wherein
each output circuit includes a shift register circuit and a delay circuit disposed at a subsequent stage of the shift register circuit, and
an output terminal of the shift register circuit is electrically connected to the one of conductive electrodes of the control transistor and the delay circuit.
8. The drive circuit according to claim 1 , wherein the connection wiring is in a floating state when the control transistor is in an off state.
9. The drive circuit according to claim 1 , wherein
the connection wiring includes a first connection wiring and a second connection wiring,
the other conductive electrode of the first transistor is electrically connected to the first connection wiring,
the other conductive electrode of the second transistor is electrically connected to the second connection wiring, and
the first connection wiring and the second connection wiring are electrically connected to each other through a resistor.
10. The drive circuit according to claim 9 , wherein
the other conductive electrodes of a plurality of the first transistors are connected to the one first connection wiring,
the other conductive electrodes of a plurality of the second transistors are connected to the one second connection wiring, and
the resistor is disposed between the first connection wiring and the second connection wiring.
11. The drive circuit according to claim 9 , wherein a resistance value of the resistor is adjusted such that an inclination is formed in a signal waveform of the gate-on voltage.
12. A display device comprising:
a display panel provided with a plurality of gate lines; and
the drive circuit according to claim 1 .
13. A display device comprising:
a display panel provided with a plurality of gate lines; and
the drive circuit according to claim 9 ,
wherein the drive circuit and the resistor are separately disposed on a substrate constituting the display panel.
14. A drive circuit comprising:
a first output circuit that outputs a gate-on voltage and a gate-off voltage to a first gate line;
a second output circuit that outputs the gate-on voltage and the gate-off voltage to a second gate line disposed in a scanning direction with respect to the first gate line;
a first transistor in which one of conductive electrodes is electrically connected to the first gate line while another conductive electrode is electrically connected to the second gate line; and
a second transistor in which one of conductive electrodes is electrically connected to the second output circuit while another conductive electrode is electrically connected to a control electrode of the first transistor, the control electrode being connected to a control line through which a control signal is supplied,
wherein after the first output circuit outputs the gate-on voltage to the first gate line, the control signal is supplied to the control line and the second transistor is put into an on state to put the first transistor into the on state so as to electrically connect the first gate line and the second gate line.