Method and apparatus for data transmission in a tee system

1. A computer-implemented method for data transmission in a trusted execution environment (TEE) system, wherein:

the TEE system comprises a TEE side and a non-TEE side,

the non-TEE side comprises a shared memory, the shared memory comprises a first address, a second address, and a plurality of consecutive third addresses, wherein the first address stores a write offset address, the write offset address indicates a writeable start address in the plurality of consecutive third addresses, the second address stores a read offset address, the read offset address indicates a readable start address in the plurality of consecutive third addresses, and the plurality of consecutive third addresses store data from the TEE side, wherein the shared memory further comprises a fourth address used to store a quantity of pieces of discarded data, and

wherein the method is executed by a first thread on the TEE side, the computer-implemented method comprising:

obtaining first data;

switching to the non-TEE side by calling a predetermined function by using the first data as an input parameter;

obtaining the write offset address by reading the first address;

obtaining the read offset address by reading the second address;

determining whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, wherein the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte;

if the quantity of bytes of the first data is less than or equal to the quantity of writable bytes,

writing the first data into the plurality of consecutive third addresses starting from the write offset address;

updating the write offset address in the first address; and

returning to the TEE side;

if the quantity of bytes of the first data is greater than the quantity of writable bytes,

discarding the first data; and

incrementing the quantity of pieces of discarded data stored in the fourth address by one.

2. The computer-implemented method of claim 1 , wherein the first data comprise one or more of logs, monitoring data, or statistical data.

3. The computer-implemented method of claim 1 , further comprising performing waiting if the quantity of bytes of the first data is greater than the quantity of writable bytes.

4. The computer-implemented method of claim 1 , wherein the quantity of pieces of discarded data is an atomic variable.

5. The computer-implemented method of claim 1 , wherein the write offset address is before the read offset address, and a quantity of writeable bytes is equal to a difference obtained by subtracting the write offset address from the read offset address.

6. The computer-implemented method of claim 1 , wherein the write offset address is after the read offset address, and the quantity of writable bytes is equal to a difference obtained by subtracting a quantity of unwritable bytes from a quantity of the plurality of consecutive third addresses, wherein the quantity of unwritable bytes is equal to a difference obtained by subtracting the read offset address from the write offset address.

7. The computer-implemented method of claim 1 , wherein the write offset address is the same as the read offset address, and a quantity of writeable bytes is equal to a quantity of all the plurality of consecutive third addresses.

8. The computer-implemented method of claim 1 , wherein the TEE system comprises an SGX system, and the predetermined function comprises an OCall function.

9. A computer-implemented system in a trusted execution environment (TEE) system, wherein:

the TEE system comprises a TEE side and a non-TEE side,

the non-TEE side comprises a shared memory, the shared memory comprises a first address, a second address, and a plurality of consecutive third addresses, wherein the first address stores a write offset address, the write offset address indicates a writeable start address in the plurality of consecutive third addresses, the second address stores a read offset address, the read offset address indicates a readable start address in the plurality of consecutive third addresses, and the plurality of consecutive third addresses store data from the TEE side, wherein the shared memory further comprises a fourth address used to store a quantity of pieces of discarded data, and

the TEE side comprises one or more processors serving for a first thread operating on the TEE side; and one or more computer memory devices interoperably coupled with the one or more processors and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more processors, perform one or more operations comprising:

obtaining first data;

switching to the non-TEE side by calling a predetermined function by using the first data as an input parameter;

obtaining the write offset address by reading the first address;

obtaining the read offset address by reading the second address;

determining whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, wherein the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte;

if the quantity of bytes of the first data is less than or equal to the quantity of writable bytes,

writing the first data into the plurality of consecutive third addresses starting from the write offset address;

updating the write offset address in the first address; and

returning to the TEE side;

if the quantity of bytes of the first data is greater than the quantity of writable bytes,

discarding the first data; and

incrementing the quantity of pieces of discarded data stored in the fourth address by one.

10. The computer-implemented system of claim 9 , wherein the first data comprise one or more of logs, monitoring data, or statistical data.

11. The computer-implemented system of claim 9 , wherein the one or more operations further comprise performing waiting if the quantity of bytes of the first data is greater than the quantity of writable bytes.

12. The computer-implemented system of claim 9 , wherein the quantity of pieces of discarded data is an atomic variable.

13. The computer-implemented system of claim 9 , wherein the write offset address is before the read offset address, and a quantity of writeable bytes is equal to a difference obtained by subtracting the write offset address from the read offset address.

14. The computer-implemented system of claim 9 , wherein the write offset address is after the read offset address, and the quantity of writable bytes is equal to a difference obtained by subtracting a quantity of unwritable bytes from a quantity of the plurality of consecutive third addresses, wherein the quantity of unwritable bytes is equal to a difference obtained by subtracting the read offset address from the write offset address.

15. The computer-implemented system of claim 9 , wherein the write offset address is the same as the read offset address, and a quantity of writeable bytes is equal to a quantity of all the plurality of consecutive third addresses.

16. The computer-implemented system of claim 9 , wherein the TEE system comprises an SGX system, and the predetermined function comprises an OCall function.

17. A non-transitory, computer-readable medium storing one or more instructions executable by one or more processors serving for a first thread operating on a trusted execution environment (TEE) side in a TEE system, wherein:

the TEE system comprises the TEE side and a non-TEE side,

the non-TEE side comprises a shared memory, the shared memory comprises a first address, a second address, and a plurality of consecutive third addresses, wherein the first address stores a write offset address, the write offset address indicates a writeable start address in the plurality of consecutive third addresses, the second address stores a read offset address, the read offset address indicates a readable start address in the plurality of consecutive third addresses, and the plurality of consecutive third addresses store data from the TEE side, wherein the shared memory further comprises a fourth address used to store a quantity of pieces of discarded data, and

the TEE side comprises the one or more processors; and

the one or more instructions, when executed by the one or more processors, perform one or more operations comprising:

obtaining first data;

switching to the non-TEE side by calling a predetermined function by using the first data as an input parameter;

obtaining the write offset address by reading the first address;

obtaining the read offset address by reading the second address;

determining whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, wherein the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte;

if the quantity of bytes of the first data is less than or equal to the quantity of writable bytes,

writing the first data into the plurality of consecutive third addresses starting from the write offset address;

updating the write offset address in the first address; and

returning to the TEE side;

if the quantity of bytes of the first data is greater than the quantity of writable bytes,

discarding the first data; and

incrementing the quantity of pieces of discarded data stored in the fourth address by one.

18. The non-transitory, computer-readable medium of claim 17 , wherein the one or more instructions further comprise performing waiting if the quantity of bytes of the first data is greater than the quantity of writable bytes.