IP Library Granted Patent US 11,422,421
Granted Patent B2
US 11,422,421 · App. 16/785,554 · Granted Aug 23, 2022

Liquid crystal display

Inventors: Young Jae Jeon (Asan-si, KR); Shin Tack Kang (Yongin-si, KR); Su In Kim (Gunpo-si, KR); Ju Yong Park (Asan-si, KR); Gi Jung Lee (Asan-si, KR); Sol Ip Jeong (Cheonan-si, KR)
G02F1/136286G02F1/13624H01L27/124
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Quick Facts
Patent No.
US 11,422,421
App. No.
16/785,554
Granted
Aug 23, 2022
Kind
B2
Abstract

A liquid crystal display includes a gate line; a data line crossing the gate line; a first voltage line spaced apart from the gate line; a second voltage line, a first transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode; a second transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode; a third transistor including a third gate electrode connected to the first voltage line, a third source electrode connected to the second drain electrode, and a third drain electrode connected to the second voltage line; a first liquid crystal capacitor connected to the first drain electrode of the first transistor; and a second liquid crystal capacitor connected to the second drain electrode of the second transistor.

Claims (46)

1. A liquid crystal display comprising:

a gate line;

a data line crossing the gate line;

a first voltage line spaced apart from the gate line;

a second voltage line spaced apart from the data line and disposed in a different layer from the first voltage line, the second voltage line overlapping and crossing the first voltage line;

a third voltage line spaced apart from the gate line and opposing the first voltage line with respect to the gate line therebetween;

a first transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode;

a second transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode;

a third transistor including a third gate electrode connected to the first voltage line, a third source electrode connected to the second drain electrode, and a third drain electrode directly connected to the second voltage line;

a first liquid crystal capacitor connected to the first drain electrode of the first transistor; and

a second liquid crystal capacitor connected to the second drain electrode of the second transistor,

wherein the second voltage line is disposed in a middle of the adjacent data lines and overlaps the gate line, the first voltage line, and the third voltage line,

wherein the first voltage line includes first and second elongated parts connected at ends of first voltage line and extending along a same direction as the second voltage line, and the third voltage line includes third and fourth elongated parts connected at ends of third voltage line and extending along the same direction as the second voltage line, and

wherein the third gate electrode opposes the third voltage line with respect to the gate line therebetween.

2. The liquid crystal display of claim 1 , wherein

the first transistor and the second transistor include a first semiconductor, and

the third transistor includes a second semiconductor spaced apart from the first semiconductor.

3. The liquid crystal display of claim 2 , wherein

the first gate electrode and the second gate electrode are connected to each other to form a gate electrode,

the first semiconductor overlaps the gate electrode, and

the second semiconductor overlaps the third gate electrode.

4. The liquid crystal display of claim 3 , wherein

an edge of the first semiconductor is disposed inside an edge of the gate electrode and the gate line in a plan view, and

the edge of the first semiconductor is spaced apart from the edge of the gate electrode and the gate line.

5. The liquid crystal display of claim 4 , wherein

an edge of the second semiconductor is disposed inside an edge of the third gate electrode and the first voltage line in the plan view, and

the edge of the second semiconductor is spaced apart from the edge of the third gate electrode and the first voltage line.

6. The liquid crystal display of claim 3 , wherein

the gate line extends in a first direction,

the first source electrode and the second source electrode include two first branches respectively extending in a second direction perpendicular to the first direction,

the first drain electrode includes a second branch disposed between the two first branches, and a first extended part connected to the second branch, and

the second drain electrode includes a third branch extending in the second direction, and a second extended part connected to the third branch.

7. The liquid crystal display of claim 6 , wherein

the second voltage line is spaced apart from the data line and is disposed in a same conductive layer as the data line, and

the third drain electrode extends in the second direction.

8. The liquid crystal display of claim 7 , wherein

the first extended part and the second extended part are faced each other with respect to the gate line in a plan view.

9. The liquid crystal display of claim 8 , wherein

one terminal end of the first liquid crystal capacitor includes a first sub-pixel electrode electrically connected to the first drain electrode,

one terminal end of the second liquid crystal capacitor includes a second sub-pixel electrode electrically connected to the second drain electrode, and

the first sub-pixel electrode and the second sub-pixel electrode are faced each other with respect to the gate line in a plan view.

10. The liquid crystal display of claim 9 ,

wherein the first extended part overlaps the third voltage line to form a first storage capacitor, and

the second extended part overlaps the first voltage line to form a second storage capacitor.

11. The liquid crystal display of claim 3 , wherein

a voltage transmitted by the first voltage line and a voltage transmitted by the second voltage line are constant.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: JEON, YOUNG JAE; KANG, SHIN TACK; KIM, SU IN; PARK, JU YONG; LEE, GI JUNG; JEONG, SOL IP
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 051856/0104 →
Priority Claims (1)
KR 10-2019-0056889 · May 15, 2019 · national
Continuity (1)
Related Publication 20200363689A1 · Nov 19, 2020