Method and apparatus for interpreting bytecode instruction stream

1. A computer-implemented method for interpreting an instruction stream, the method comprising:

receiving, by one or more processors of an interpreter of a virtual machine, an instruction stream comprising a plurality of machine instructions;

reading, by the one or more processors, a first value stored in a first register corresponding to a current instruction of the plurality of machine instructions, the first value comprising a current analog function address;

determining, by the one or more processors, that the first value is valid;

in response to determining, by the one or more processors, that the first value is valid, storing the first value in a second register, wherein the second register is configured to store current analog function addresses corresponding to current instructions in the instruction stream;

retrieving, by the one or more processors and from a memory, a subsequent analog function address corresponding to a subsequent instruction associated with the current instruction by using the current analog function address;

storing, by the one or more processors, the subsequent analog function address in the first register; and

executing, by the one or more processors, the current instruction based on the current analog function address read from the second register.

2. The computer-implemented method of claim 1 , wherein the current instruction corresponding to the first value is different from a jump instruction.

3. The computer-implemented method of claim 1 , wherein retrieving the subsequent analog function address comprises:

determining an operation code corresponding to the subsequent instruction; and

querying a mapping table stored in the memory to retrieve the subsequent analog function address corresponding to the operation code.

4. The computer-implemented method of claim 3 , wherein determining the operation code corresponding to the subsequent instruction comprises:

accumulating a program counter value of a program counter by a value of a predetermined byte length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

5. The computer-implemented method of claim 3 , wherein determining the operation code corresponding to the subsequent instruction comprises:

determining an instruction length of the current instruction;

accumulating a program counter value of a program counter by the instruction length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

6. The computer-implemented method of claim 1 , further comprising:

determining, based on the subsequent analog function address, whether a subsequent analog function corresponding to the subsequent instruction is loaded into a cache; and

in response to that the subsequent analog function corresponding to the subsequent instruction is not loaded into the cache, loading the subsequent analog function into the cache.

7. The computer-implemented method of claim 1 , wherein the instruction stream comprises a bytecode instruction stream obtained through compiling by using a smart contract.

8. A non-transitory computer-readable medium storing one or more instructions executable by a computer system to perform operations for interpreting an instruction stream, the operations comprising:

receiving an instruction stream comprising a plurality of machine instructions;

reading a first value stored in a first register corresponding to a current instruction of the plurality of machine instructions, the first value comprising a current analog function address;

determining that the first value is valid;

in response to determining that the first value is valid, storing the first value in a second register, wherein the second register is configured to store current analog function addresses corresponding to current instructions in the instruction stream;

retrieving, from a memory, a subsequent analog function address corresponding to a subsequent instruction associated with the current instruction by using the current analog function address;

storing the subsequent analog function address in the first register; and

executing the current instruction based on the current analog function address read from the second register.

9. The non-transitory computer-readable medium of claim 8 , wherein the current instruction corresponding to the first value is different from a jump instruction.

10. The non-transitory computer-readable medium of claim 8 , wherein retrieving the subsequent analog function address comprises:

determining an operation code corresponding to the subsequent instruction; and

querying a mapping table stored in the memory to retrieve the subsequent analog function address corresponding to the operation code.

11. The non-transitory computer-readable medium of claim 10 , wherein determining the operation code corresponding to the subsequent instruction comprises:

accumulating a program counter value of a program counter by a value of a predetermined byte length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

12. The non-transitory computer-readable medium of claim 10 , wherein determining the operation code corresponding to the subsequent instruction comprises:

determining an instruction length of the current instruction;

accumulating a program counter value of a program counter by the instruction length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

13. The non-transitory computer-readable medium of claim 8 , the operations further comprising:

determining, based on the subsequent analog function address, whether a subsequent analog function corresponding to the subsequent instruction is loaded into a cache; and

in response to that the subsequent analog function corresponding to the subsequent instruction is not loaded into the cache, loading the subsequent analog function into the cache.

14. The non-transitory computer-readable medium of claim 8 , wherein the instruction stream comprises a bytecode instruction stream obtained through compiling by using a smart contract.

15. A computer-implemented system, comprising:

one or more computers; and

one or more computer memory devices interoperably coupled with the one or more computers and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more computers, perform operations for interpreting an instruction stream, the operations comprising:

receiving an instruction stream comprising a plurality of machine instructions;

reading a first value stored in a first register corresponding to a current instruction of the plurality of machine instructions, the first value comprising a current analog function address;

determining that the first value is valid;

in response to determining that the first value is valid, storing the first value in a second register, wherein the second register is configured to store current analog function addresses corresponding to current instructions in the instruction stream;

retrieving, from a memory, a subsequent analog function address corresponding to a subsequent instruction associated with the current instruction by using the current analog function address;

storing the subsequent analog function address in the first register; and

executing the current instruction based on the current analog function address read from the second register.

16. The computer-implemented system of claim 15 , wherein the current instruction corresponding to the first value is different from a jump instruction.

17. The computer-implemented system of claim 15 , wherein retrieving the subsequent analog function address comprises:

determining an operation code corresponding to the subsequent instruction; and

querying a mapping table stored in the memory to retrieve the subsequent analog function address corresponding to the operation code.

18. The computer-implemented system of claim 17 , wherein determining the operation code corresponding to the subsequent instruction comprises:

accumulating a program counter value of a program counter by a value of a predetermined byte length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

19. The computer-implemented system of claim 17 , wherein determining the operation code corresponding to the subsequent instruction comprises:

determining an instruction length of the current instruction;

accumulating a program counter value of a program counter by the instruction length to obtain a location number of the subsequent instruction; and

querying, based on the location number, an instruction sequence table stored in the memory to obtain the operation code corresponding to the subsequent instruction.

20. The computer-implemented system of claim 15 , the operations further comprising:

determining, based on the subsequent analog function address, whether a subsequent analog function corresponding to the subsequent instruction is loaded into a cache; and

in response to that the subsequent analog function corresponding to the subsequent instruction is not loaded into the cache, loading the subsequent analog function into the cache.