Methods and apparatus for a delta-sigma analog-to-digital converter
Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.
1. An incremental delta-sigma analog-to-digital converter (ADC), comprising:
a sample-and-hold circuit comprising a first switch, a second switch, a first capacitor, and an amplifier; and
an integrator comprising the first capacitor, a second capacitor, and the amplifier;
wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.
2. The incremental delta-sigma ADC according to claim 1 , further comprising a digital-to-analog converter connected to the integrator.
3. The incremental delta-sigma ADC according to claim 1 , wherein the first capacitor is directly connected between the first switch and an input terminal of the amplifier.
4. The incremental delta-sigma ADC according to claim 1 , wherein the second switch is directly connected to the first capacitor and an output terminal of the amplifier.
5. The incremental delta-sigma ADC according to claim 1 , wherein the second capacitor is directly connected between the first switch and an output terminal of the amplifier.
6. The incremental delta-sigma ADC according to claim 1 , wherein the integrator further comprises a resistor:
directly connected in series with the first capacitor and
directly connected to the first switch.
7. The incremental delta-sigma ADC according to claim 1 , wherein the first switch is connected in series with the second capacitor.
8. The incremental delta-sigma ADC according to claim 1 , wherein the first capacitor is connected in series with the amplifier.
9. The incremental delta-sigma ADC according to claim 1 , wherein the second switch is connected in parallel with the amplifier.
10. A method for operating on an input signal with a delta-sigma analog-to-digital converter (ADC), wherein the input signal has a voltage, comprising:
sampling the input signal comprising closing a first switch and a second switch;
charging a first capacitor to the voltage of the input signal;
holding the charge of the first capacitor comprising:
opening the first switch and second switch; and
applying a high impedance to the first capacitor using an amplifier; and
summing an output voltage from a signal converter and the voltage of the first capacitor;
integrating the summed voltage using a second capacitor in parallel with the amplifier.
11. The method according to claim 10 , wherein the first capacitor is connected directly between the first switch and an input terminal of the amplifier.
12. The method according to claim 10 , wherein the second switch is connected in parallel with the amplifier.
13. The method according to claim 10 , wherein the first switch is connected in series with the second capacitor.
14. A system configured to receive an input signal having a voltage, comprising:
a sample-and-hold circuit comprising a first switch, a second switch, a first capacitor, and an amplifier, and configured to:
receive the input signal;
sample the input signal comprising operating the first switch and the second switch;
charge the first capacitor to the voltage of the input signal;
hold the charge of the first capacitor comprising:
operating the first switch and second switch; and
applying a high impedance to the first capacitor using the amplifier; and
a first integrator comprising the first capacitor, a second capacitor, and the amplifier, and configured to integrate a summed voltage using the second capacitor and the amplifier, wherein the summed voltage is a sum of an output voltage of a digital-to-analog converter and the voltage of the first capacitor;
wherein the sample-and-hold circuit and the first integrator share the first capacitor and the amplifier.
15. The system according to claim 14 , wherein the first capacitor is directly connected between the first switch and an input terminal of the amplifier.
16. The system according to claim 14 , wherein the second switch is:
directly connected to the first capacitor and an output terminal of the amplifier; and is connected in parallel with the amplifier.
17. The system according to claim 14 , wherein the first switch is connected in series with the second capacitor.
18. The system according to claim 14 , wherein the second capacitor is directly connected between the first switch and an output terminal of the amplifier.
19. The system according to claim 14 , wherein the amplifier comprises a p-channel transistor connected in series with an n-channel transistor.
20. The system according to claim 14 , further comprising a second integrator connected to an output terminal of the first integrator.