Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder
A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.
1. A memory system comprising:
a memory device including a plurality of memory sets; and
a controller including a decoder configured to:
receive multiple codewords from the plurality of memory sets;
decode the multiple codewords;
determine an inter-set delay for a codeword of a select memory set;
when the inter-set delay is greater than a maximum inter-set delay,
determine a total decoding time based on an effective inter-set delay and an effective decoding latency; and
output the decoded codeword at the end of the total decoding time,
wherein each of the plurality of memory sets includes multiple namespaces, each namespace including a plurality of logical blocks.
2. The memory system of claim 1 , wherein the inter-set delay includes a latency from a time that the decoder starts decoding for the select memory set in a previous round to a time that the decoder starts decoding for the select memory set in a current round.
3. The memory system of claim 1 , wherein the decoder outputs the decoded codeword in response to a data valid signal, which is generated at the end of the total decoding time.
4. The memory system of claim 1 , wherein, when the inter-set delay is less than or equal to the maximum inter-set delay, the decoder determines the total decoding time based on the inter-set delay and a decoding time associated with the decoding of the codeword.
5. The memory system of claim 1 , wherein the decoder sequentially receives the multiple codewords from the plurality of memory sets in a set order.
6. The memory system of claim 5 , wherein the set order is an order of a round-robin scheme.
7. The memory system of claim 1 , wherein the effective inter-set delay is determined as the difference between the inter-set delay and a set value, and the effective decoding latency is determined as the sum of the decoding time and the set value.
8. The memory system of claim 7 , wherein the set value is the same as the difference value between an actual maximum inter-set delay and an allowed maximum inter-set delay when the inter-set delay is greater than or equal to the difference value, and the set value is determined as zero when the inter-set delay is less than the difference value.
9. A method for operating a decoder comprising:
receiving multiple codewords from a plurality of memory sets;
decoding the multiple codewords;
determining an inter-set delay for a codeword of a select memory set;
when the inter-set delay is greater than a maximum inter-set delay, determining a total decoding time based on an effective inter-set delay and an effective decoding latency; and
outputting the decoded codeword at the end of the total decoding time,
wherein each of the plurality of memory sets includes multiple namespaces, each namespace including a plurality of logical blocks.
10. The method of claim 9 , wherein the inter-set delay includes a latency from a time that the decoder starts decoding for the select memory set in a previous round to a time that the decoder starts decoding for the select memory set in a current round.
11. The method of claim 9 , wherein the outputting of the decoded codeword includes outputting the decoded codeword in response to a data valid signal, which is generated at the end of the total decoding time.
12. The method of claim 9 , wherein the determining of the total decoding time includes determining the total decoding time based on the inter-set delay and a decoding time associated with the decoding of the codeword when the inter-set delay is less than or equal to the maximum inter-set delay.
13. The method of claim 9 , wherein the decoding of the multiple codewords includes sequentially receiving the multiple codewords from the plurality of memory sets in a set order.
14. The method of claim 13 , wherein the set order is an order of a round-robin scheme.
15. The method of claim 9 , further comprising:
determining the effective inter-set delay as the difference between the inter-set delay and a set value, and
determining the effective decoding latency is determined as the sum of the decoding time and the set value.
16. The method of claim 15 , further comprising:
determining the set value as the difference value between an actual maximum inter-set delay and an allowed maximum inter-set delay when the inter-set delay is greater than or equal to the difference value, and
determining the set value as zero when the inter-set delay is less than the difference value.