IP Library Granted Patent US 11,347,520
Granted Patent B2
US 11,347,520 · App. 16/789,994 · Granted May 31, 2022

Unavailable memory device initialization system

Inventors: Chih-Chung Chen (New Taipei, TW); Shih-Hao Wang (New Taipei, TW)
Assignee: Dell Products L.P.
G06F9/4408G06F9/4411G06F12/0238G06F12/126G06F13/1689
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Quick Facts
Patent No.
US 11,347,520
App. No.
16/789,994
Granted
May 31, 2022
Kind
B2
Abstract

An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem. Subsequently, during second initialization operations and based on the respective unavailable memory device identifier(s) stored in the non-volatile storage subsystem, the BIOS engine generates a memory overlay that hides each unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

Claims (55)

1. An unavailable memory device initialization system, comprising:

a memory system;

a memory controller device that is coupled to the memory system and configured to:

determine, during initialization operations, whether the memory system includes unavailable memory devices; and

a Basic Input/Output System (BIOS) engine that is coupled to the memory system and the memory controller device, wherein the BIOS engine is configured to:

identify, during first initialization operations, at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations;

store, during the first initialization operations in a non-volatile storage subsystem in response to identifying the at least one unavailable memory device, respective unavailable memory device identifiers associated with each at least one unavailable memory device; and

generate, during second initialization operations that are subsequent to the first initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, a memory overlay that hides each at least one unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

2. The system of claim 1 , wherein the identifying the at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations includes:

identifying a respective Memory Reference Code (MRC) training error determined by the memory controller device during the first initialization operations for each at least one unavailable memory device.

3. The system of claim 1 , wherein the generating the memory overlay includes:

providing, during the second initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, respective memory overlay values in a memory overlay database for each unavailable memory device identifiers.

4. The system of claim 1 , wherein each at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations is identified by a respective unavailable memory device channel associated with that unavailable memory device.

5. The system of claim 1 , wherein the BIOS engine is configured to:

automatically cause, subsequent to storing the respective unavailable memory device identifiers associated with each at least one unavailable memory device in the non-volatile storage subsystem during the first initialization operations, a reboot that begins the second initialization operations.

6. The system of claim 1 , wherein the BIOS engine is configured to:

identify, during the second initialization operations in the non-volatile storage subsystem, the respective unavailable memory device identifiers;

provide, for display in response to identifying the respective unavailable memory device identifiers in the non-volatile storage subsystem, an initialization proceed request; and

complete, in response to receiving an affirmative response to the initialization proceed request, the second initialization operations such that a runtime environment is provided.

7. An Information Handling System (IHS), comprising:

a processing system; and

a memory system that is coupled to the processing system and that includes instructions that, when executed by the processing system, cause the processing system to provide a Basic Input/Output System (BIOS) engine that is configured to:

identify, during first initialization operations, at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by a memory controller device during the first initialization operations;

store, during the first initialization operations in a non-volatile storage subsystem in response to identifying the at least one unavailable memory device, respective unavailable memory device identifiers associated with each at least one unavailable memory device; and

generate, during second initialization operations that are subsequent to the first initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, a memory overlay that hides each at least one unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

8. The IHS of claim 7 , wherein the identifying the at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations includes:

identifying a respective Memory Reference Code (MRC) training error determined by the memory controller device during the first initialization operations for each at least one unavailable memory device.

9. The IHS of claim 7 , wherein the generating the memory overlay includes:

providing, during the second initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, respective memory overlay values in a memory overlay database for each unavailable memory device identifiers.

10. The IHS of claim 7 , wherein each at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations is identified by a respective unavailable memory device channel associated with that unavailable memory device.

11. The IHS of claim 7 , wherein the BIOS engine is configured to:

automatically cause, subsequent to storing the respective unavailable memory device identifiers associated with each at least one unavailable memory device in the non-volatile storage subsystem during the first initialization operations, a reboot that begins the second initialization operations.

12. The IHS of claim 7 , wherein the BIOS engine is configured to:

identify, during the second initialization operations in the non-volatile storage subsystem, the respective unavailable memory device identifiers;

provide, for display in response to identifying the respective unavailable memory device identifiers in the non-volatile storage subsystem, an initialization proceed request; and

complete, in response to receiving an affirmative response to the initialization proceed request, the second initialization operations such that a runtime environment is provided.

13. The IHS of claim 12 , wherein the BIOS engine is configured to:

erase, during the second initialization operations, the respective unavailable memory device identifiers from the non-volatile storage subsystem.

14. A method for initializing a computing device including an unavailable memory device, comprising:

identifying, by a BIOS engine provide by a processing system during first initialization operations, at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by a memory controller device during the first initialization operations;

storing, by the BIOS engine during the first initialization operations in a non-volatile storage subsystem in response to identifying the at least one unavailable memory device, respective unavailable memory device identifiers associated with each at least one unavailable memory device; and

generating, by the BIOS engine during second initialization operations that are subsequent to the first initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, a memory overlay that hides each at least one unavailable memory device from the memory controller device such that the memory controller device determines that the memory system does not include any unavailable memory devices during the second initialization operations.

15. The method of claim 14 , wherein the identifying the at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations includes:

identifying a respective Memory Reference Code (MRC) training error determined by the memory controller device during the first initialization operations for each at least one unavailable memory device.

16. The method of claim 14 , wherein the generating the memory overlay includes:

providing, during the second initialization operations and based on the respective unavailable memory device identifiers stored in the non-volatile storage subsystem, respective memory overlay values in a memory overlay database for each unavailable memory device identifiers.

17. The method of claim 14 , wherein each at least one unavailable memory device that is included in the memory system and that was determined to be unavailable by the memory controller device during the first initialization operations is identified by a respective unavailable memory device channel associated with that unavailable memory device.

18. The method of claim 14 , further comprising:

automatically causing, by the BIOS engine subsequent to storing the respective unavailable memory device identifiers associated with each at least one unavailable memory device in the non-volatile storage subsystem during the first initialization operations, a reboot that begins the second initialization operations.

19. The method of claim 14 , further comprising:

identifying, by the BIOS engine during the second initialization operations in the non-volatile storage subsystem, the respective unavailable memory device identifiers;

providing, by the BIOS engine for display in response to identifying the respective unavailable memory device identifiers in the non-volatile storage subsystem, an initialization proceed request; and

completing, by the BIOS engine in response to receiving an affirmative response to the initialization proceed request, the second initialization operations such that a runtime environment is provided.

20. The method of claim 19 , further comprising:

erase, by the BIOS engine during the second initialization operations, the respective unavailable memory device identifiers from the non-volatile storage subsystem.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2020
From: CHEN, CHIH-CHUNG; WANG, SHIH-HAO
To: DELL PRODUCTS L.P.
Reel/Frame 051813/0332 →