IP Library Granted Patent US 11,201,105
Granted Patent B2
US 11,201,105 · App. 16/790,933 · Granted Dec 14, 2021

Semiconductor package having a spacer with a junction cooling pipe

Inventors: Seungwon Im (Bucheon-si, KR); Oseob Jeon (Seoul, KR); Byoungok Lee (Bucheon-si, KR); Yoonsoo Lee (Incheon, KR); Joonseo Son (Seoul, KR); Dukyong Lee (Cheon-an, KR); Changyoung Park (Ilsan-si, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/433H01L23/13H01L23/4334H01L23/473H01L23/49568H01L23/49861H01L25/0657H01L23/24H01L2224/33
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Quick Facts
Patent No.
US 11,201,105
App. No.
16/790,933
Granted
Dec 14, 2021
Kind
B2
Abstract

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

Claims (26)

1. A semiconductor package comprising:

a first substrate coupled to a first die;

a second substrate coupled to a second die; and

a spacer comprised within a perimeter of the first substrate and within a perimeter of the second substrate, the spacer coupled directly to and between the first die and the second die through a solder, the spacer comprising a junction cooling pipe therethrough.

2. The package of claim 1 , wherein a wall of the junction cooling pipe comprises a dielectric material.

3. The package of claim 1 , the spacer further comprising a plurality of junction cooling pipes therethrough, a cross section of the plurality of junction cooling pipes fully comprised within a cross section of the spacer.

4. The package of claim 1 , further comprising a second spacer between the second die and a third die, the third die coupled to the second substrate.

5. The package of claim 1 , further comprising;

a third substrate coupled to a third die;

a fourth substrate coupled to a fourth die; and

a second spacer coupled between and coupled to the third die and the fourth die, the second spacer comprising a junction cooling pipe therethrough;

wherein a face of the second substrate is coupled to a face of the third substrate.

6. The package of claim 1 , wherein the junction cooling pipe comprises a finned heat exchanger, one of integrally formed therewith or coupled thereto.

7. A semiconductor package comprising:

a first substrate coupled to a first die;

a second substrate coupled to a second die; and

a spacer comprised within a perimeter of the first substrate and within a perimeter of the second substrate, the spacer coupled directly to and between the first die and the second die through a solder, the spacer comprising a junction cooling pipe.

8. The package of claim 7 , wherein a wall of the junction cooling pipe comprises a dielectric material.

9. The package of claim 7 , the spacer further comprising a plurality of junction cooling pipes therethrough, a cross section of the plurality of junction cooling pipes fully comprised within a cross section of the spacer.

10. The package of claim 7 , further comprising a second spacer between the second die and a third die, the third die coupled to the second substrate.

11. The package of claim 7 , further comprising;

a third substrate coupled to a third die;

a fourth substrate coupled to a fourth die; and

a second spacer coupled between and coupled to the third die and the fourth die, the second spacer comprising a junction cooling pipe therethrough;

wherein a face of the second substrate is coupled to a face of the third substrate.

12. The package of claim 7 , wherein the junction cooling pipe comprises a finned heat exchanger, one of integrally formed therewith or coupled thereto.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: IM, SEUNGWON; JEON, OSEOB; LEE, BYOUNGOK; LEE, YOONSOO; LEE, DUKYONG; SON, JOONSEO; PARK, CHANGYOUNG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051819/0982 →