IP Library Granted Patent US 11,619,955
Granted Patent B2
US 11,619,955 · App. 16/793,878 · Granted Apr 4, 2023

Thermostat power wire switching circuit

Inventors: Hyunki Kim (Rogers, MN); Robert D. Juntunen (Minnetonka, MN)
Assignee: Ademco Inc.
G05D23/19F24F11/88H03K17/689H03K17/6871H03K17/6877F24F11/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,619,955
App. No.
16/793,878
Granted
Apr 4, 2023
Kind
B2
Abstract

A switch circuit configured to receive power from either a single power source or dual power source. The circuit includes two power input terminals and two power output terminals. For a single power source, the switch circuit may receive the single power source at either of the two power input terminals. The switch circuit provides power to a load without regard to which of the power input terminals the single power source is connected. The switch circuit shorts the power output terminals for a single power input, which provides power at both power output terminals. For a dual power source system, the switch circuit may isolate the two power output terminals so each power output terminal may operate independently without shorting. In some examples, the switch circuit may be part of a thermostat or similar HVAC system controller.

Claims (63)

1. A circuit for receiving power from a heating, ventilation, and air-conditioning device, the circuit comprising:

a first switching circuit comprising:

a first input terminal;

a first output terminal;

a first switch with a first control terminal; and

a first control node; and

a second switching circuit comprising:

a second input terminal;

a second output terminal electrically connected to the first output terminal;

a second switch with a second control terminal connected to the first control node; and

a second control node connected to the first control terminal;

wherein:

in response to receiving a voltage at the first input terminal, the first switching circuit is configured to control the second switch via the first control node to isolate the second input terminal from the second output terminal, and

in response to receiving a voltage at the second input terminal, the second switching circuit is configured to control the first switch via the second control node to isolate the first input terminal from the first output terminal.

2. The circuit of claim 1 , further comprising a first power output terminal and a second power output terminal, wherein each of the first power output terminal and the second power output terminal is configured to output power received at the first input terminal in response to receiving the voltage at the first input terminal and receiving a voltage of approximately zero volts at the second input terminal.

3. The circuit of claim 1 , further comprising a first power output terminal and a second power output terminal, wherein each of the first power output terminal and the second power output terminal is configured to output power received at the second input terminal in response to receiving the voltage at the second input terminal without receiving a voltage at the first input terminal.

4. The circuit of claim 1 , further comprising a first power output terminal and a second power output terminal, wherein, in response to receiving both a first voltage at the first input terminal and a second voltage at the second input terminal:

the circuit is configured to isolate the first power output terminal from the second power output terminal;

the first power output terminal is configured to output a first power received at the first input terminal; and

second power output terminal is configured to output a second power received at the second input terminal.

5. The circuit of claim 1 , further comprising a transistor driver circuit wherein the transistor driver circuit isolates the first power output terminal and the second power output terminal from the first switching circuit and the second switching circuit.

6. The circuit of claim 5 , wherein the isolation comprises galvanic isolation.

7. The circuit of claim 5 , wherein the isolation comprises capacitive isolation.

8. The circuit of claim 1 , further comprising power stealing circuitry.

9. A system for controlling heating, ventilation and air conditioning (HVAC) equipment, the system comprising:

one or more processors configured to receive signals from one or more sensors;

a switch circuit configured to provide power to the system and the one or more processors, the switch circuit comprising:

a first switching circuit comprising:

a first input terminal;

a first output terminal;

and

a second switching circuit comprising:

a second input terminal;

a second output terminal electrically connected to the first output terminal;

wherein:

in response to receiving a voltage at the first input terminal, the first switching circuit is configured to isolate the second input terminal from the second output terminal, and

in response to receiving a voltage at the second input terminal, the second switching circuit is configured to isolate the first input terminal from the first output terminal.

10. The system of claim 9 , wherein:

a first switching circuit comprising:

a first switch with a first control terminal; and

a first control node; and

a second switching circuit comprising:

a second switch with a second control terminal connected to the first control node; and

a second control node connected to the first control terminal;

wherein:

in response to receiving a voltage at the first input terminal, the first switching circuit is configured to control the second switch via the first control node to isolate the second input terminal from the second output terminal, and

in response to receiving a voltage at the second input terminal, the second switching circuit is configured to control the first switch via the second control node to isolate the first input terminal from the first output terminal.

11. The system of claim 9 , wherein the switch circuit further comprises a first power output terminal and a second power output terminal, wherein each of the first power output terminal and a second power output terminal is configured to output power received at the first input terminal in response to receiving the voltage at the first input terminal and receiving a voltage of approximately zero volts at the second input terminal.

12. The system of claim 9 , wherein the switch circuit further comprises a first power output terminal and a second power output terminal, wherein each of the first power output terminal and a second power output terminal is configured to output power received at the second input terminal in response to receiving the voltage at the second input terminal and receiving a voltage of approximately zero volts at the first input terminal.

13. The system of claim 9 , wherein the switch circuit further comprises a first power output terminal and a second power output terminal, wherein, in response to receiving both a first voltage at the first input terminal and a second voltage at the second input terminal:

the switch circuit is configured to isolate the first power output terminal from the second power output terminal;

the first power output terminal is configured to output a first power received at the first input terminal; and

second power output terminal is configured to output a second power received at the second input terminal.

14. The system of claim 9 , wherein the switch circuit further comprises a transistor driver circuit wherein the transistor driver circuit isolates the first power output terminal and the second power output terminal from the first switching circuit and the second switching circuit.

15. A method comprising:

receiving, by a switch circuit, a first voltage at a first input terminal, wherein the first voltage is an alternating current (AC) voltage; and in response to receiving the first voltage at the first input terminal, outputting a control signal to a first control terminal, wherein the control signal electrically disconnects a second input terminal from a transistor driver circuit.

16. The method of claim 15 , further comprising:

in response to receiving the first voltage at the first input terminal, outputting a direct current (DC) voltage to the transistor driver circuit; and

in response to receiving the DC voltage, turning ON a transistor pair, wherein turning ON the transistor pair electrically connects a first power output terminal to a second power output terminal, wherein the first input terminal is electrically connected to the first output terminal.

17. The method of claim 15 , further comprising:

in response to receiving the first voltage at the first input terminal at the same time as a second voltage at the second input terminal, isolating a first power output terminal from a second power output terminal, wherein:

the first input terminal is electrically connected to the first power output terminal, and

the second input terminal is electrically connected to the second power output terminal.

Assignments (3)
CHANGE OF NAME Recorded Jun 12, 2025
From: ADEMCO INC.
To: RESIDEO LLC
Reel/Frame 071546/0001 →
SECURITY INTEREST Recorded Apr 1, 2022
From: BRK BRANDS, INC.; ADEMCO INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 059571/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2020
From: KIM, HYUNKI; JUNTUNEN, ROBERT D.
To: ADEMCO INC.
Reel/Frame 051850/0155 →