IP Library Granted Patent US 11,093,174
Granted Patent B1
US 11,093,174 · App. 16/794,404 · Granted Aug 17, 2021

Information handling system having improved host memory buffer for input/output requests

Inventors: Young Hwan Jang (Gwangju-si, KR); Lip Vui Kan (Hillbrooks, SG)
Assignee: Dell Products L.P.
G06F3/0659G06F3/068G06F3/0611G06F12/0866G06F2212/1024
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Quick Facts
Patent No.
US 11,093,174
App. No.
16/794,404
Granted
Aug 17, 2021
Kind
B1
Abstract

A host memory buffer is configured as a write cache for prioritizing read operations. When a peripheral device (such as a solid-state drive) receives a mixture of read requests and write requests, the write requests may be suspended or deferred to first execute the read requests. The write requests may be cached to the host memory buffer, thus allowing the peripheral device to process the read requests for relatively immediate response. Once the read requests are completed, the peripheral device may begin executing a queue of the write requests stored to the host memory buffer. This caching strategy results in a thirty percent (30%) improvement in drive performance.

Claims (41)

1. A method, comprising:

configuring, an external host memory buffer operating in a host memory device of a host as a dedicated cache memory exclusively used by the solid-state drive;

receiving a read request sent via an input/output channel from the host requesting the solid-state drive to read a first data;

receiving a write request sent via the input/output channel from the host requesting the solid-state drive to write a second data to an internal cache memory operating in the solid-state drive;

suspending an execution of the write request received via the input/output channel from the host;

prioritizing the read request by caching the write request via the input/output channel to the external host memory buffer operating in the host memory device of the host as the dedicated cache memory exclusively used by the solid-state drive;

reading the first data by executing the read request;

in response to the executing of the read request, retrieving the write request cached to the external host memory buffer via the input/output channel from the host memory device of the host as the dedicated cache memory exclusively used by the solid-state drive; and

executing the write request to write the second data to the internal cache memory operating in the solid-state drive.

2. The method of claim 1 , further comprising retrieving a mapping information associated with the read request.

3. The method of claim 1 , further comprising retrieving a mapping information associated with the write request.

4. The method of claim 1 , further comprising executing an operating system.

5. The method of claim 1 , further comprising queuing the write request.

6. The method of claim 1 , further comprising sending the write request to the external host memory buffer.

7. An information handling system comprising:

a hardware processor; and

a memory device accessible to the hardware processor, the memory device storing instructions that when executed by the hardware processor perform operations, the operations including:

configuring a portion of the memory device as an external dedicated cache memory exclusively used by a solid-state drive;

sending a read request via an input/output channel to the solid-state drive requesting to read a first data from an internal cache memory operating in the solid-state drive;

sending a write request via the input/output channel to the solid-state drive requesting to write a second data to the internal cache memory operating in the solid-state drive;

receiving a cache request sent via the input/output channel from the solid-state drive requesting to cache the write request to the portion of the memory device configured as the external dedicated cache memory exclusively used by the solid-state drive;

executing the read request to read the first data;

in response to the executing of the read request, retrieving the write request cached to the portion of the memory device configured as the external dedicated cache memory exclusively used by the solid-state drive; and

executing the write request to write the second data to the internal cache memory operating in the solid-state drive.

8. The system of claim 7 , wherein the operations further include retrieving a mapping information associated with the read request.

9. The system of claim 7 , wherein the operations further include retrieving a mapping information associated with the write request.

10. The system of claim 7 , wherein the operations further include executing an operating system.

11. The system of claim 7 , wherein the operations further include suspending the write request.

12. The system of claim 7 , wherein the operations further include queuing the write request.

13. A memory device storing instructions that when executed by a processor perform operations, the operations including:

configuring a portion of a host memory buffer operating in a host as an external dedicated cache memory exclusively used by a solid-state drive;

receiving a read request sent via an input/output channel from the host requesting to read a first data from an internal cache memory operating in the solid-state drive;

receiving a write request sent via the input/output channel from the host requesting to write a second data to the internal cache memory operating in the solid-state drive;

suspending an execution of the write request received via the input/output channel from the host;

prioritizing the read request by caching the write request via the input/output channel to the portion of the host memory buffer operating in the host as the external dedicated cache memory exclusively used by the solid-state drive;

in response to executing the read request, retrieving the write request via the input/output channel from the portion of the host memory buffer operating in the host as the external dedicated cache memory exclusively used by the solid-state drive; and

executing the write request.

14. The memory device of claim 13 , wherein the operations further include retrieving a mapping information associated with the read request.

15. The memory device of claim 13 , wherein the operations further include retrieving a mapping information associated with the write request.

16. The memory device of claim 15 , wherein the operations further include executing an operating system.

17. The memory device of claim 13 , wherein the operations further include queuing the write request.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2020
From: JANG, YOUNG HWAN; KAN, LIP VUI
To: DELL PRODUCTS, LP
Reel/Frame 051855/0676 →