System and method to reduce host interrupts for non-critical errors

1. An information handling system, comprising:

a baseboard management controller;

a device configured to provide a System Management Interrupt (SMI) in response to an error on the device;

a processor configured to receive the SMI, to enter a System Management Mode (SMM) in response to receiving the SMI, and to execute first interrupt handler code in SMM, wherein the first interrupt handler code operates to:

determine that the SMI is associated with a non-critical error on the device;

provide interrupt information associated with the SMI in response to determining that the SMI is associated with the non-critical error on the device; and

exit SMM to a runtime mode; and

a runtime agent configured to receive the interrupt information during the runtime mode and to provide the interrupt information to the baseboard management controller to execute second interrupt handler code to service the non-critical error on the device;

wherein in executing the second interrupt handler code, the baseboard management controller is configured to read a Machine Specific Register of the processor via a Platform Environment Control Interface.

2. The information handling system of claim 1 , wherein the first interrupt handler code further operates to:

determine that the SMI is associated with a critical error on the device;

service the critical error on the device; and

exit SMM to the runtime mode.

3. The information handling system of claim 1 , wherein the device comprises a memory controller.

4. The information handling system of claim 3 , wherein the memory controller is configured to provide the SMI in response to an uncorrectable memory error, and wherein the uncorrectable memory error is a critical error.

5. The information handling system of claim 3 , wherein the memory controller is configured to provide the SMI in response to a correctable memory error, and wherein the correctable memory error is the non-critical error.

6. A method, comprising:

receiving, by a processor of an information handling system, a System Management Interrupt (SMI) in response to an error on a device of the information handling system;

entering a System Management Mode (SMM) in response to receiving the SMI;

executing first interrupt handler code in SMM, wherein in executing the first interrupt handler code, the method further comprises:

determining that the SMI is associated with a non-critical error on the device;

providing interrupt information associated with the SMI in response to determining that the SMI is associated with the non-critical error on the device; and

exiting SMM to a runtime mode;

receiving, by a runtime agent of the information handling system, the interrupt information during the runtime mode;

receiving, by a baseboard management controller of the information handling system, the interrupt information from the runtime agent;

executing, by the information handling system, second interrupt handler code to service the non-critical error on the device; and

reading, by the baseboard management controller, a Machine Specific Register of the processor via a Platform Environment Control Interface in response to receiving the interrupt information.

7. The method of claim 6 , further comprising:

determining, by the first interrupt handler code, that the SMI is associated with a critical error on the device;

servicing, by the first interrupt handler, the critical error on the device; and

exiting SMM to the runtime mode.

8. The method of claim 6 , wherein the device comprises a memory controller.

9. The method of claim 8 , wherein the memory controller is configured to provide the SMI in response to an uncorrectable memory error, and wherein the uncorrectable memory error is a critical error.

10. The method of claim 8 , wherein the memory controller is configured to provide the SMI in response to a correctable memory error, and wherein the correctable memory error is the non-critical error.

11. An information handling system, comprising:

a device configured to provide an interrupt in response to an error on the device;

a baseboard management controller configured to receive the interrupt from the device, and to execute first interrupt handler code to:

determine that the interrupt is associated with a non-critical error on the device;

service the non-critical error on the device in response to determining that the interrupt is associated with the non-critical error;

determine that the interrupt is associated with a critical error on the device;

provide a System Management Interrupt (SMI) associated with the critical error in response to determining that the interrupt is associated with the critical error; and

read a Machine Specific Register of the processor via a Platform Environment Control Interface in response to receiving the interrupt; and

a processor configured to enter a System Management Mode (SMM) in response to receiving the SMI, and to execute second interrupt handler code in SMM, wherein the second interrupt handler code operates to:

service the critical error on the device; and

exit SMM.

12. The information handling system of claim 11 , wherein the device comprises a memory controller.

13. The information handling system of claim 12 , wherein the memory controller is configured to provide the SMI in response to an uncorrectable memory error.

14. The information handling system of claim 13 , wherein the memory controller is configured to provide the SMI in response to a correctable memory error.

15. The information handling system of claim 14 , wherein the uncorrectable memory error is the critical error, and wherein the correctable memory error is the non-critical error.