Biasing scheme for power amplifiers
A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.
1. A front-end module comprising:
a bias network including a current mirror;
a junction temperature sensor;
an n-bit analog-to-digital converter;
an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions; and
a power amplifier;
the bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier being integrated on a first semiconductor die.
2. The front-end module of claim 1 wherein the bias network includes a hybrid bias current topology of constant and proportional to square of temperature (PTAT2) current generators.
3. The front-end module of claim 1 wherein the bias network includes a multi-stacked topology.
4. The front-end module of claim 1 wherein the power amplifier is a Silicon-On-Insulator (SOI) complementary metal-oxide-semiconductor (CMOS) power amplifier.
5. The front-end module of claim 1 wherein the power amplifier is configured to provide an output power of at least 22 dBm.
6. The front-end module of claim 1 wherein the power amplifier includes an n-channel metal-oxide field-effect transistor (NMOSFET).
7. The front-end module of claim 1 wherein the power amplifier is configured to provide a gain flatness of less than 1 dB over a temperature range of −40° C. to 125° C.
8. The front-end module of claim 1 wherein the power amplifier is configured to operate at a first level during transmit modes and operate at a second level during non-transmit modes.
9. The front-end module of claim 1 wherein the n-bit current source bank is configured to set reference current levels for without feedback loops.
10. The front-end module of claim 1 wherein the one or more temperature regions includes 2 n +2 temperature regions.
11. The front-end module of claim 1 wherein the n-bit current source bank is a proportional to absolute temperature (PTAT) current source bank.
12. The front-end module of claim 1 wherein the current mirror is a sub-threshold region current mirror.
13. A semiconductor die comprising:
a bias network including a current mirror;
a junction temperature sensor;
an n-bit analog-to-digital converter;
an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions; and
a power amplifier.
14. The semiconductor die of claim 13 wherein the bias network includes a hybrid bias current topology of constant and proportional to square of temperature (PTAT2) current generators.
15. The semiconductor die of claim 13 wherein the bias network includes a multi-stacked topology.
16. The semiconductor die of claim 13 wherein the power amplifier is a Silicon-On-Insulator (SOI) complementary metal-oxide-semiconductor (CMOS) power amplifier.
17. The semiconductor die of claim 13 wherein the power amplifier includes an n-channel metal-oxide field-effect transistor (NMOSFET).
18. The semiconductor die of claim 13 wherein the power amplifier is configured to operate at a first level during transmit modes and operate at a second level during non-transmit modes.
19. The semiconductor die of claim 13 wherein the n-bit current source bank is configured to set reference current levels for without feedback loops.
20. The semiconductor die of claim 13 wherein the one or more temperature regions includes 2 n +2 temperature regions.