IP Library Granted Patent US 10,963,419
Granted Patent B1
US 10,963,419 · App. 16/802,961 · Granted Mar 30, 2021

System and method for handling in-band interrupts on inactive I3C channels

Inventors: Jordan Chin (Austin, TX); Timothy M. Lambert (Austin, TX)
Assignee: Dell Products, L.P.
G06F13/4291G06F11/349G06F13/24G06F13/4068H04L12/403H04L61/2038G06F2213/0016
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Quick Facts
Patent No.
US 10,963,419
App. No.
16/802,961
Granted
Mar 30, 2021
Kind
B1
Abstract

A multiplexor for an Improved Inter-Integrated Circuit (I3C) network includes a switch, a snooper, and an I3C slave module coupled to an I3C master interface. The switch selectably couples I3C busses to the I3C master interface. Each I3C bus includes I3C slave interfaces. The selected I3C bus is the active bus, and the non-selected I3C busses are inactive buses. The snooper detects In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses. When the snooper receives a first IBI on an inactive bus, the snooper provides an indication. The I3C slave module provides a second IBI to the I3C master interface in response to the indication.

Claims (44)

1. A multiplexor for an Improved Inter-Integrated Circuit (I3C) network, the multiplexor comprising:

a switch to couple a first I3C master interface to a selectable one of a plurality of I3C buses, each I3C bus being coupled to a plurality of I3C slave interfaces, a selected one of the I3C buses being an active bus, and the non-selected ones of the I3C busses being inactive buses;

a snooper to detect In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses, the snooper configured to receive a first IBI from a first I3C slave interface coupled to a first inactive bus, and to provide an indication when the first MI is received, the first I3C slave interface having a first I3C address; and

an I3C slave module coupled to the first I3C master interface, and configured to receive the indication and to provide a second IBI to the first I3C master interface in response to the indication, the I3C slave module having a second I3C address.

2. The multiplexor of claim 1 , wherein, in providing the second IBI, the I3C slave module is further configured to provide the second I3C address to the first I3C master interface.

3. The multiplexor of claim 2 , wherein in providing the second IBI, the I3C slave module is further configured to provide a data payload indicating that the first IBI was provided on the first inactive bus.

4. The multiplexor of claim 3 , wherein the I3C slave module is further configured to receive a reply from the first I3C master interface in response to the second IBI, the reply including an instruction for the switch to decouple a first active bus from the first I3C master interface and to couple the first inactive bus to the first I3C master interface.

5. The multiplexor of claim 1 , further comprising:

a second I3C master interface configured to determine the first I3C address in response to receiving the first IBI.

6. The multiplexor of claim 5 , wherein the second I3C master interface is further configured to provide the first I3C address to the I3C slave module.

7. The multiplexor of claim 6 , wherein, in providing the second IBI, the I3C slave module is further configured to provide the first I3C address to the second I3C master interface.

8. The multiplexor of claim 7 , wherein the multiplexor is configured to decouple a first active bus from the first I3C master interface and to couple the first inactive bus to the second I3C master interface in response to providing the first I3C address to the second I3C master interface.

9. A method for an improved inter-integrated circuit (I3C) network, the method comprising:

coupling, by a switch of an I3C multiplexor, a first I3C master interface to a selectable one of a plurality of I3C buses, each I3C bus being coupled to a plurality of I3C slave interfaces, the selected one of the I3C buses being an active bus, and the non-selected ones of the I3C busses being inactive buses;

detecting, by a snooper of the I3C multiplexor, a first In-Band Interrupts (MI) from a first I3C slave interface coupled to a first inactive bus, the first I3C slave interface having a first I3C address;

providing an indication that the first IBI was received;

receiving, by an I3C slave module of the I3C multiplexor, the indication; and

providing a second IBI to the first I3C master interface in response to the indication.

10. The method of claim 9 , wherein, in providing the second IBI, the method further comprises:

providing, by the I3C slave module, the first I3C address to the first I3C master interface.

11. The method of claim 10 , wherein, in providing the second IBI, the method further comprises:

providing, by the I3C slave module, a data payload indicating that the first IBI was provided on the first inactive bus.

12. The method of claim 11 , further comprising:

receiving, by the I3C slave module, a reply from the first I3C master interface in response to the second IBI, the reply including an instruction for the switch to decouple a first active bus from the first I3C master interface and to couple the first inactive bus to the first I3C master interface.

13. The method of claim 9 , further comprising:

determining, by a second I3C master interface of the I3C multiplexor, the first I3C address in response to receiving the first IBI.

14. The method of claim 13 , further comprising:

providing, by the second I3C master, the first I3C address to the I3C slave module.

15. The method of claim 14 , wherein, in providing the second IBI, the method further comprises:

providing, by the I3C slave module, the first I3C address to the second I3C master interface.

16. The method of claim 15 , further comprising:

decoupling, by the I3C multiplexor, a first active bus from the first I3C master interface in response to providing the first I3C address to the second I3C master interface; and

coupling the first inactive bus to the second I3C master interface.

17. An information handling system, comprising:

a first I3C master interface; and

a multiplexor for an I3C network, the multiplexor including:

a switch to couple the first I3C master interface to a selectable one of a plurality of I3C buses, each I3C bus being coupled to a plurality of I3C slave interfaces, a selected one of the I3C buses being an active bus, and the non-selected ones of the I3C busses being inactive buses;

a snooper to detect In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses, the snooper configured to receive a first IBI from a first I3C slave interface coupled to a first inactive bus, and to provide an indication when the first IBI is received, the first I3C slave interface having a first I3C address; and

an I3C slave module coupled to the first I3C master interface, and configured to provide a second IBI to the first I3C master interface in response to the indication, the I3C slave module having a second I3C address.

18. The information handling system of claim 17 , wherein, in providing the second IBI, the I3C slave module is further configured to provide the second I3C address to the first I3C master interface.

19. The information handling system of claim 17 wherein:

the multiplexor further comprises a second I3C master interface configured to determine the first I3C address in response to receiving the first IBI, and to provide the first I3C address to the I3C slave module; and

in providing the second IBI, the I3C slave module is further configured to provide the first I3C address to the second I3C master interface.

20. The information handling system of claim 19 , wherein the multiplexor is configured to decouple a first active bus from the first I3C master interface and to couple the first inactive bus to the second I3C master interface in response to providing the first I3C address to the second I3C master interface.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2020
From: CHIN, JORDAN; LAMBERT, TIMOTHY M.
To: DELL PRODUCTS, LP
Reel/Frame 051949/0566 →
Cited By (1)
US 12,579,087