Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages
Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
1. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the first reference voltage comprises a ground voltage.
2. The apparatus of claim 1 wherein the body connection line comprises a length dimension that extends perpendicularly to the lateral direction.
3. The apparatus of claim 1 wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are the same reference voltage.
4. The apparatus of claim 1 wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are different reference voltages.
5. The apparatus of claim 1 wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are a ground voltage.
6. The apparatus of claim 1 wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage comprising a common plate voltage.
7. The apparatus of claim 1 wherein:
the conductive region is a bitline that extends along a plane, and
the body connection line extends substantially parallel to the bitline.
8. The apparatus of claim 1 wherein the body connection line comprises a conductivity type opposite to the source/drain region source/drain regions.
9. The apparatus of claim 1 wherein the conductive region is a bitline, and further comprising a spacing region that spaces the bitline from the body connection line.
10. The apparatus of claim 1 wherein the spacing region is configured as a line that extends substantially parallel to the body connection line.
11. The apparatus of claim 1 wherein the body connection line comprises semiconductor material.
12. The apparatus of claim 1 wherein the body connection line comprises doped semiconductor material.
13. The apparatus of claim 1 further comprising pocket regions along the body connection line.
14. The apparatus of claim 13 wherein the pocket regions comprises higher charge carrier concentration than other region of the body connection line.
15. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are the same reference voltage.
16. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are a ground voltage.
17. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the second transistor comprises a body region, and further comprising:
a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are a common plate voltage.
18. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein:
the conductive region is a bitline that extends along a plane; and
the body connection line extends substantially parallel to the bitline.
19. An apparatus, comprising;
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the body connection line comprises a conductivity type opposite to the source/drain regions.
20. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the conductive region is a bitline, and further comprising a spacing region that spaces the bitline from the body connection line.
21. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein a spacing region is configured as a line that extends substantially parallel to the body connection line.
22. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the body connection line comprises semiconductor material.
23. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
wherein the body connection line comprises doped semiconductor material.
24. An apparatus, comprising:
a memory cell comprising two vertical transistors and one capacitor;
the two vertical transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;
the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor;
a body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage; and
pocket regions along the body connection line.
25. The apparatus of claim 24 wherein the pocket regions comprises higher charge carrier concentration than other region of the body connection line.