Self-aligned and robust IGBT devices

1. A method of forming a vertical insulated gate bipolar transistor (IGBT) device, comprising:

providing a semiconductor substrate of n conductivity type having a front side and a backside;

forming column structures of p conductivity type fully surrounding an active region in the front side of the semiconductor substrate, forming each column structure including:

forming a column trench in the front side of the semiconductor substrate, the trench including trench side walls and a trench floor,

forming dielectric spacers on the trench side walls,

forming a column deep region extending downwardly from the trench floor by applying dopants of p conductivity type into the semiconductor substrate through the trench floor,

filling the trench with poly silicon of p conductivity type which is in contact with the column deep region; and

depositing an oxide layer including silicon oxide onto the front side of the semiconductor substrate including the column trenches filled with the poly silicon;

planarizing the oxide layer;

depositing an etch stop layer including silicon nitride on the oxide layer;

applying a photomask on the etch stop layer; and

forming a plurality of metal-oxide-semiconductor field-effect transistor (MOSFET) cells in the active region fully surrounded by the column structures,

wherein the substrate of n conductivity type is common to the plurality of MOSFET cells formed in the active area, and

wherein the column structures are substantially deeper than the MOSFET cells to protect the cells from high voltage.

2. The method of claim 1 , wherein forming the plurality of MOSFET cells include forming p body contact trenches and MOSFET gate trenches for each MOSFET cell via the photomask, wherein both the contact trenches and the gate trenches are formed using the photomask to self-align the contact trenches with the gate trenches.

3. The method of claim 2 , wherein forming the p body contact trenches and the MOSFET gate trenches include etching p-body contact trenches and the MOSFET gate trenches simultaneously with the same mask about 0.5 μm depth, and filling the p-body contact trenches with oxide to stop further etching while the MOSFET gate trenches being etched down up to 3-6 μm depth.

4. The method of claim 3 further including:

applying a photoresist mask including a contact mask, the contact mask enabling removal of oxide from the p-body contact trenches, and

implanting p+ dopant which is aligned at the center of each p-body formed so that the threshold of the at least one MOSFET cell is not affected.

5. The method of claim 4 further including processing the backside of the semiconductor substrate after applying a pad mask to the front side of the semiconductor substrate, the processing the backside including:

grinding the backside in the range of 2 to 5 mils thickness for 600 Volt and 1200 Volt IGBT device manufacturing,

wet etching to remove silicon damages after the grinding, and

forming n-buffer region and p/p+ hole injection region on the backside by implanting n-type and p-type implants into the backside,

activating backside implants, and

applying backside metal.

6. The method of claim 5 , wherein the backside implant activation is done by one of low temperature tube, rapid thermal annealing (RTA) and laser annealing.