System and method for variable input output voltage on different channels for increasing power efficiency
An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (V ddq ) setting for bidirectional communications with the CPU.
1. An information handling system having improved power efficiency, comprising:
a processing unit including a dual in-line memory module (DIMM) controller and configured to host a basic input output system (BIOS);
a first set of DIMMs that are connected to the DIMM controller by a first communication channel; and
a second set of DIMMs that are connected to the DIMM controller by a second communication channel,
wherein the BIOS is configured to provide a unique data bus input output voltage (V ddq ) setting for bidirectional communications between each DIMM in the first and second sets of DIMMs and the processing unit, wherein the DIMM controller is configured to supply a particular amount of V ddq to each DIMM based on the provided unique V ddq setting, wherein the particular amount of V ddq varies from a default amount of V ddq based on whether a channel length between the DIMM controller and a corresponding DIMM is greater than or less than a trace length threshold.
2. The information handling system of claim 1 , wherein the DIMM controller includes a first transceiver (TX/RX) with a first voltage regulator (VR) and a second TX/RX with a second VR, wherein the first TX/RX and the second TX/RX are connected to the first set of DIMMs and to the second set of DIMMs, respectively, through the corresponding first communication channel and second communication channel.
3. The information handling system of claim 2 , wherein the first VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the first TX/RX and to a data bus IO pin of each DIMM in the first set of DIMMs.
4. The information handling system of claim 2 , wherein the second VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the second TX/RX and to a data bus IO pin of each DIMM in the second set of DIMMs.
5. The information handling system of claim 1 , wherein the V ddq is referenced to a ground terminal.
6. The information handling system of claim 1 further comprising a baseband management controller that is configured to obtain a DIMM serial presence detect (SPD) information from each DIMM in the first and second set of DIMMs.
7. The information handling system of claim 6 , wherein the unique V ddq setting for each DIMM is based on the obtained SPD information of the DIMM.
8. The information handling system of claim 1 , wherein the BIOS receives an identification of a voltage regulator that is configured to supply the particular amount of V ddq .
9. The information handling system of claim 8 , wherein the BIOS utilizes a look-up table to generate the unique V ddq setting based on the received identification.
10. The information handling system of claim 8 , wherein the voltage regulator is configured to supply a logic circuit voltage to each DIMM in the first set of DIMMs and the second set of DIMMs.
11. The information handling system of claim 10 , wherein the V ddq and the logic circuit voltage are supplied using separate voltage rails.
12. A method, comprising:
hosting, by a processing unit, a basic input output system (BIOS), wherein the processing unit includes a dual in-line memory module (DIMM) controller;
connecting a first set of DIMMs and a second set of DIMMs to the DIMM controller by a first communication channel and a second communication channel, respectively; and
providing, by the BIOS, a unique data bus input output voltage (V ddq ) setting for bidirectional communications between each DIMM in the first and second sets of DIMMs and the processing unit, wherein the DIMM controller is configured to supply a particular amount of V ddq to each DIMM based on the provided unique V ddq setting, wherein the particular amount of V ddq varies from a default amount of V ddq based on whether a channel length between the DIMM controller and a corresponding DIMM is greater than or less than a trace length threshold.
13. The method of claim 12 , wherein the DIMM controller includes a first transceiver (TX/RX) with a first voltage regulator (VR) and a second TX/RX with a second VR, wherein the first TX/RX and the second TX/RX are connected to the first set of DIMMs and to the second set of DIMMs, respectively, through the corresponding first communication channel and second communication channel.
14. The method of claim 13 , wherein the first VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the first TX/RX and to a data bus IO pin of each DIMM in the first set of DIMMs.
15. The method of claim 13 , wherein the second VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the second TX/RX and to a data bus IO pin of each DIMM in the second set of DIMMs.
16. The method of claim 12 , wherein the V ddq is referenced to a ground terminal.
17. The method of claim 12 further comprising: supplying, by the DIMM controller, a logic circuit voltage to each DIMM in the first set of DIMMs and the second set of DIMMs.
18. The method of claim 17 , wherein the V ddq and the logic circuit voltage are supplied using separate voltage rails.
19. An information handling system, comprising:
a processing unit including a dual in-line memory module (DIMM) controller and configured to host a basic input output system (BIOS), wherein the DIMM controller includes a first transceiver (TX/RX) with a first voltage regulator (VR) and a second TX/RX with a second VR;
a first set of DIMMs that are connected to the first TX/RX by a first communication channel; and
a second set of DIMMs that are connected to the second TX/RX by a second communication channel,
wherein the BIOS is configured to provide a unique data bus input output voltage (V ddq ) setting for bidirectional communications between each DIMM in the first and second sets of DIMMs and the processing unit, wherein each one of the first VR and the second VR is configured to supply a particular amount of V ddq to each associated DIMM based on the provided unique V ddq setting, wherein the particular amount of V ddq varies from a default amount of V ddq based on whether a channel length between the DIMM controller and a corresponding DIMM is greater than or less than a trace length threshold.
20. The information handling system of claim 19 , wherein the first VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the first TX/RX and to a data bus IO pin of each DIMM in the first set of DIMMs while the second VR is configured to supply the particular amount of V ddq to a data bus input output (IO) pin of the second TX/RX and to a data bus IO pin of each DIMM in the second set of DIMMs.