Verifying basic input/output system (BIOS) boot block code
Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.
1. In an Information Handling System (IHS) comprising a processor; a memory coupled to the processor, the memory comprising Basic Input/Output System (BIOS) instructions stored thereon; and an embedded controller (EC) coupled to the memory, a method comprising:
unlocking, by the EC, write access to the memory after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on;
performing, by the EC, an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions;
identifying, by the EC, an error in a bit of the BIOS boot block code; and
providing, by the EC, a visual indication of the error via a Light-Emitting Diode (LED).
2. The method of claim 1 , wherein the EC is configured to unlock write access to the memory via a general-purpose input/output (GPIO) interface before an SLP_S3 signal is asserted during the power-on sequence.
3. The method of claim 2 , wherein the EC is configured to unlock write access to the memory prior to the BIOS instructions executing a reset vector.
4. The method of claim 3 , wherein the EC is configured to unlock write access to the memory prior to execution of an authenticated code module (ACM).
5. The method of claim 4 , wherein the ECC evaluation is performed individually upon each of a plurality of sub-portions of the BIOS boot block code portion.
6. The method of claim 1 , wherein to verify the integrity of a given sub-portion of the BIOS boot block code portion, the EC is further configured to compare a hash of the given sub-portion with a corresponding hash derived during BIOS binary image creation.
7. An embedded controller (EC) coupled to a memory of an Information Handling System (IHS), wherein the memory includes Basic Input/Output System (BIOS) code executable by a processor of the IHS, the EC having program instructions stored thereon that, upon execution by the EC, cause the IHS to:
after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory;
perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS code;
identify a first error in a bit of the BIOS boot block code;
toggle a value of the bit;
perform another ECC evaluation of the BIOS boot block code;
identify another error; and
provide a visual indication of the error via a Light-Emitting Diode (LED).
8. The EC of claim 7 , wherein the EC is configured to unlock write access to the memory via a general-purpose input/output (GPIO) interface before an SLP_S3 signal is asserted during the power-on sequence.
9. The EC of claim 8 , wherein the EC is configured to unlock write access to the memory prior to the BIOS instructions executing a reset vector.
10. The EC of claim 9 , wherein the EC is configured to unlock write access to the memory prior to execution of an authenticated code module (ACM).
11. The EC of claim 7 , wherein to verify the integrity of a given sub-portion of the BIOS boot block code portion, the EC is further configured to compare a hash of the given sub-portion with a corresponding hash derived during BIOS binary image creation.